Re: [PATCH] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes

[Abel Vesa]

On 26-06-26 09:46:03, Krishna Chaitanya Chundru wrote:
> 
> 
> On 6/25/2026 3:42 PM, Abel Vesa wrote:
> > On 26-06-10 17:40:09, Krishna Chaitanya Chundru wrote:
> >> Eliza supports two PCIe instances: one 8GT/s x1 (PCIe0) and one 8GT/s x2
> >> (PCIe1). Add PCIe controller and PHY nodes for both instances, and update
> >> the GCC clock references to use the newly added PHY nodes instead of
> >> placeholder zeros.
> >>
> >> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> >> ---
> >> This patch depends on https://lore.kernel.org/all/20260608-eliza-v3-0-9bdeb7434b28@xxxxxxxxxxxxxxxx/
> >> ---
> >>  arch/arm64/boot/dts/qcom/eliza.dtsi | 359 +++++++++++++++++++++++++++++++++++-
> >>  1 file changed, 357 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
> >> index 7e97361a5dc5..2a51da62270d 100644
> >> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
> >> @@ -610,8 +610,8 @@ gcc: clock-controller@100000 {
> >>  
> >>  			clocks = <&bi_tcxo_div2>,
> >>  				 <&sleep_clk>,
> >> -				 <0>,
> >> -				 <0>,
> >> +				 <&pcie0_phy>,
> >> +				 <&pcie1_phy>,
> >>  				 <&ufs_mem_phy 0>,
> >>  				 <&ufs_mem_phy 1>,
> >>  				 <&ufs_mem_phy 2>,
> >> @@ -716,6 +716,361 @@ mmss_noc: interconnect@1780000 {
> >>  			#interconnect-cells = <2>;
> >>  		};
> >>  
> >> +		pcie0: pcie@1c00000 {
> >> +			device_type = "pci";
> >> +			compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550";
> >> +			reg = <0 0x01c00000 0 0x3000>,
> >> +			      <0 0x40000000 0 0xf1d>,
> >> +			      <0 0x40000f20 0 0xa8>,
> >> +			      <0 0x40001000 0 0x1000>,
> >> +			      <0 0x40100000 0 0x100000>,
> >> +			      <0 0x01c03000 0 0x1000>;
> >> +			reg-names = "parf",
> >> +				    "dbi",
> >> +				    "elbi",
> >> +				    "atu",
> >> +				    "config",
> >> +				    "mhi";
> >> +			#address-cells = <3>;
> >> +			#size-cells = <2>;
> >> +			ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
> >> +				 <0x02000000 0 0x40300000 0 0x40300000 0 0x3d00000>;
> >> +
> >> +			interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
> >> +			interrupt-names = "msi0",
> >> +					  "msi1",
> >> +					  "msi2",
> >> +					  "msi3",
> >> +					  "msi4",
> >> +					  "msi5",
> >> +					  "msi6",
> >> +					  "msi7",
> >> +					  "global";
> >> +
> >> +			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> >> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> >> +				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> >> +				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> >> +				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> >> +				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
> >> +				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> >> +				 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
> >> +			clock-names = "aux",
> >> +				      "cfg",
> >> +				      "bus_master",
> >> +				      "bus_slave",
> >> +				      "slave_q2a",
> >> +				      "ddrss_sf_tbu",
> >> +				      "noc_aggr",
> >> +				      "cnoc_sf_axi";
> >> +
> >> +			resets = <&gcc GCC_PCIE_0_BCR>,
> >> +				 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
> >> +			reset-names = "pci",
> >> +				      "link_down";
> >> +
> >> +			interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
> >> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> >> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> >> +					 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
> >> +			interconnect-names = "pcie-mem",
> >> +					     "cpu-pcie";
> >> +
> >> +			power-domains = <&gcc GCC_PCIE_0_GDSC>;
> >> +
> >> +			operating-points-v2 = <&pcie0_opp_table>;
> >> +
> >> +			iommu-map = <0 &apps_smmu 0x1480 0x1>,
> >> +				    <0x100 &apps_smmu 0x1481 0x1>;
> >> +
> >> +			interrupt-map = <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>,
> >> +					<0 0 0 2 &intc 0 0 0 565 IRQ_TYPE_LEVEL_HIGH>,
> >> +					<0 0 0 3 &intc 0 0 0 566 IRQ_TYPE_LEVEL_HIGH>,
> >> +					<0 0 0 4 &intc 0 0 0 567 IRQ_TYPE_LEVEL_HIGH>;
> >> +			interrupt-map-mask = <0 0 0 0x7>;
> >> +			#interrupt-cells = <1>;
> >> +
> >> +			linux,pci-domain = <0>;
> >> +			num-lanes = <1>;
> >> +			bus-range = <0 0xff>;
> >> +
> >> +			dma-coherent;
> >> +
> > No pinctrl states?
> >
> >> +
> >> +		pcie1: pcie@1c08000 {
> >> +			device_type = "pci";
> >> +			compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550";
> >> +			reg = <0 0x01c08000 0 0x3000>,
> >> +			      <0 0x44000000 0 0xf1d>,
> >> +			      <0 0x44000f20 0 0xa8>,
> >> +			      <0 0x44001000 0 0x1000>,
> >> +			      <0 0x44100000 0 0x100000>,
> >> +			      <0 0x01c0b000 0 0x1000>;
> >> +			reg-names = "parf",
> >> +				    "dbi",
> >> +				    "elbi",
> >> +				    "atu",
> >> +				    "config",
> >> +				    "mhi";
> >> +			#address-cells = <3>;
> >> +			#size-cells = <2>;
> >> +			ranges = <0x01000000 0 0x00000000 0 0x44200000 0 0x100000>,
> >> +				 <0x02000000 0 0x44300000 0 0x44300000 0 0x3d00000>;
> >> +
> >> +			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> >> +			interrupt-names = "msi0",
> >> +					  "msi1",
> >> +					  "msi2",
> >> +					  "msi3",
> >> +					  "msi4",
> >> +					  "msi5",
> >> +					  "msi6",
> >> +					  "msi7",
> >> +					  "global";
> >> +
> >> +			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> >> +				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> >> +				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> >> +				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> >> +				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
> >> +				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
> >> +				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> >> +				 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
> >> +			clock-names = "aux",
> >> +				      "cfg",
> >> +				      "bus_master",
> >> +				      "bus_slave",
> >> +				      "slave_q2a",
> >> +				      "ddrss_sf_tbu",
> >> +				      "noc_aggr",
> >> +				      "cnoc_sf_axi";
> >> +
> >> +			resets = <&gcc GCC_PCIE_1_BCR>,
> >> +				 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
> >> +			reset-names = "pci",
> >> +				      "link_down";
> >> +
> >> +			interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
> >> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> >> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> >> +					 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
> >> +			interconnect-names = "pcie-mem",
> >> +					     "cpu-pcie";
> >> +
> >> +			power-domains = <&gcc GCC_PCIE_1_GDSC>;
> >> +
> >> +			operating-points-v2 = <&pcie1_opp_table>;
> >> +
> >> +			iommu-map = <0 &apps_smmu 0x1400 0x1>,
> >> +				    <0x100 &apps_smmu 0x1401 0x1>;
> >> +
> >> +			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
> >> +					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
> >> +					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
> >> +					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
> >> +			interrupt-map-mask = <0 0 0 0x7>;
> >> +			#interrupt-cells = <1>;
> >> +
> >> +			linux,pci-domain = <1>;
> >> +			num-lanes = <2>;
> >> +			bus-range = <0 0xff>;
> >> +
> >> +			dma-coherent;
> > No pinctrl states?
> As we are adding perst & wake gpio's in board specific file, it is better to
> add the pincntrl also
> there only.

I'll let Bjorn and Konrad reply, but most of the sm8*50.dtsi have
them. Though some of the newer platforms moved them in the board dts.