Re: [PATCH] arm64: dts: qcom: sc8280xp: Fix DWC3 core register size

[Konrad Dybcio]

On 6/26/26 5:07 PM, Xilin Wu wrote:
> The SC8280XP DWC3 core register regions are currently described as 0xcd00
> bytes, but the hardware register block extends further. In particular, the
> DWC_usb31 LLUCTL registers start at 0xd024 and are accessed by the DWC3
> driver when a controller is limited to SuperSpeed using
> maximum-speed = "super-speed".
> 
> With the shorter resource, probing such a controller can fault when the
> driver programs LLUCTL.FORCE_GEN1. Use the correct 0xd950-byte register
> size for all SC8280XP DWC3 core instances.
> 
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Fixes: 3170a2c906c6 ("arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Xilin Wu <sophon@xxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index a2bd6b10e475..d06f79b7680c 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -4034,7 +4034,7 @@ usb_2: usb@a4f8800 {
>  
>  			usb_2_dwc3: usb@a400000 {
>  				compatible = "snps,dwc3";
> -				reg = <0 0x0a400000 0 0xcd00>;
> +				reg = <0 0x0a400000 0 0xd950>;

Let's do 0xfc100, the QC glue driver already does out-of-bounds
accesses into the base+0xfxxx space..

Konrad