[PATCH v2 3/7] iio: adc: ti-ads1262: Add channel filter support

From: Kurt Borja

Date: Sun Jun 28 2026 - 01:37:18 EST


Expose per-channel filter configuration through the filter_type
attribute.

Signed-off-by: Kurt Borja <kuurtb@xxxxxxxxx>
---
drivers/iio/adc/ti-ads1262.c | 65 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-ads1262.c b/drivers/iio/adc/ti-ads1262.c
index 6103cf5a2d1624a9..ece97a0c2b1304ad 100644
--- a/drivers/iio/adc/ti-ads1262.c
+++ b/drivers/iio/adc/ti-ads1262.c
@@ -146,6 +146,14 @@ enum {
ADS1262_RUNMODE_PULSE,
};

+enum {
+ ADS1262_FILTER_SINC1,
+ ADS1262_FILTER_SINC2,
+ ADS1262_FILTER_SINC3,
+ ADS1262_FILTER_SINC4,
+ ADS1262_FILTER_FIR,
+};
+
enum {
ADS1262_DR_2_5_SPS,
ADS1262_DR_5_SPS,
@@ -201,6 +209,7 @@ struct ads1262_chip_info {

struct ads1262_channel {
u8 input[2];
+ u8 filter;
u8 gain;
u8 data_rate;
u8 reference[3];
@@ -441,7 +450,7 @@ static int ads1262_dev_read_by_cmd(struct ads1262 *st, u8 cmd, __be32 *val)
static int ads1262_channel_enable(struct ads1262 *st,
struct ads1262_channel *chan)
{
- u8 mode0, mode2, inpmux, refmux;
+ u8 mode0, mode1, mode2, inpmux, refmux;
int ret;

/* Avoid using guard() here to mitigate AB/BA deadlock warning */
@@ -449,6 +458,7 @@ static int ads1262_channel_enable(struct ads1262 *st,
mode0 = FIELD_PREP(ADS1262_MODE0_INPUT_CHOP_MASK, chan->input_chop) |
FIELD_PREP(ADS1262_MODE0_IDAC_CHOP_MASK, chan->idac_chop) |
FIELD_PREP(ADS1262_MODE0_REFREV_MASK, chan->ref_reversal);
+ mode1 = FIELD_PREP(ADS1262_MODE1_FILTER_MASK, chan->filter);
mode2 = FIELD_PREP(ADS1262_MODE2_DR_MASK, chan->data_rate) |
FIELD_PREP(ADS1262_MODE2_GAIN_MASK, chan->gain) |
FIELD_PREP(ADS1262_MODE2_BYPASS_MASK, chan->pga_bypass);
@@ -465,6 +475,11 @@ static int ads1262_channel_enable(struct ads1262 *st,
if (ret)
return ret;

+ ret = regmap_update_bits(st->regmap, ADS1262_MODE1_REG,
+ ADS1262_MODE1_FILTER_MASK, mode1);
+ if (ret)
+ return ret;
+
ret = regmap_update_bits(st->regmap, ADS1262_MODE2_REG,
ADS1262_MODE2_DR_MASK |
ADS1262_MODE2_GAIN_MASK |
@@ -682,6 +697,52 @@ static irqreturn_t ads1262_irq_handler(int irq, void *dev_id)
return IRQ_HANDLED;
}

+static int ads1262_get_filter_type(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct ads1262 *st = iio_priv(indio_dev);
+ struct ads1262_channel *chan_data;
+
+ guard(mutex)(&st->chan_lock);
+
+ chan_data = &st->channels[chan->scan_index];
+ return chan_data->filter;
+}
+
+static int ads1262_set_filter_type(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ unsigned int val)
+{
+ struct ads1262 *st = iio_priv(indio_dev);
+
+ guard(mutex)(&st->chan_lock);
+ st->channels[chan->scan_index].filter = val;
+
+ return 0;
+}
+
+static const char * const ads1262_filter_type_labels[] = {
+ [ADS1262_FILTER_SINC1] = "sinc1",
+ [ADS1262_FILTER_SINC2] = "sinc2",
+ [ADS1262_FILTER_SINC3] = "sinc3",
+ [ADS1262_FILTER_SINC4] = "sinc4",
+ [ADS1262_FILTER_FIR] = "fir",
+};
+
+static const struct iio_enum ads1262_filter_type_enum = {
+ .items = ads1262_filter_type_labels,
+ .num_items = ARRAY_SIZE(ads1262_filter_type_labels),
+ .get = ads1262_get_filter_type,
+ .set = ads1262_set_filter_type,
+};
+
+static const struct iio_chan_spec_ext_info ads1262_ext_info[] = {
+ IIO_ENUM("filter_type", IIO_SEPARATE, &ads1262_filter_type_enum),
+ IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE,
+ &ads1262_filter_type_enum),
+ { }
+};
+
static int ads1262_alloc_channels(struct ads1262 *st,
struct iio_chan_spec **channels)
{
@@ -718,6 +779,7 @@ static int ads1262_alloc_channels(struct ads1262 *st,
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.indexed = true,
.differential = true,
+ .ext_info = ads1262_ext_info,
};
}

@@ -983,6 +1045,7 @@ static int ads1262_parse_channel_node(struct ads1262 *st,
int ret;

/* Write non-zero default configuration values */
+ chan->filter = ADS1262_FILTER_FIR;
chan->data_rate = ADS1262_DR_20_SPS;

ret = fwnode_property_read_u32_array(node, "diff-channels", pins, ARRAY_SIZE(pins));

--
2.54.0