Re: [PATCH v2 3/3] arm64: dts: qcom: kodiak: Set up 4-lane DP

From: Mahadevan P

Date: Mon Jun 29 2026 - 02:59:21 EST




On 6/28/2026 5:51 PM, Dmitry Baryshkov wrote:
On Sat, Jun 27, 2026 at 09:28:47PM -0500, Bjorn Andersson wrote:
On Wed, Apr 29, 2026 at 12:10:42PM +0530, Mahadevan P wrote:
From: Mahadevan P <mahap@xxxxxxxxxxxxxxxx>

Allow up to 4 lanes for the DisplayPort link from the PHY to the

It's hard to follow your thought process here, as you didn't document
why this change should be made. Start your commit message by describing
the problem that your change is solving.

controller now the mode-switch events can reach the QMP Combo PHY.

Signed-off-by: Mahadevan P <mahadevan.p@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 0acc6917d7aa..204513a6bd89 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -5704,7 +5704,7 @@ dp_in: endpoint {
port@1 {
reg = <1>;
mdss_dp_out: endpoint {
- data-lanes = <0 1>;
+ data-lanes = <0 1 2 3>;

And as Dmitry pointed out, not all Kodiak-based boards have 4 DP-lanes
wired up.

As a bit of explanation and context for Mahadevan. The link between DP
controller and PHY is 4 lanes. Historically we have been declaring two
lanes here because the DP / USB <-> PHY interaction wasn't finalzied,
so it was not possible to use 4 lanes for DP. The issue was solved and
now most of the platforms should be able to have all 4 lanes here.
However in some cases, platforms like Herobrine use this as a quirk,
because it was impossible to describe various quirks that they have
implemented (in case of Herobrine it is a fancy 2 lane split / mux).

I'd recommend the following approach: enable 4 lanes in the kodiak.dtsi,
while, at the same time, leaving 2 lanes for the following boards (which
should keep the board-specific override for now):
- sc7280-herobrine.dtsi, it requires special handling for 2-lanes
topology
- qcm6490-particle-tachyon.dts, it might be missing a redriver
- qcs6490-thundercomm-rubikpi3.dts, it might be missing a redriver

The Tachyon and Rubik Pi 3 boards might be missing a redriver, which
would need a reprogramming to support proper 4 lanes DP (or they don't).
Anyway, that needs to be confirmed by somebody having the schematics.


Thanks, for conclusion on this, i will update the changes validate and repost.

Thanks,
Mahadevan