Re: [PATCH 1/5] arm64: dts: qcom: shikra: Add MDSS display subsystem

[Dmitry Baryshkov]

On Mon, 29 Jun 2026 at 10:25, Nabige Aala <nabige.aala@xxxxxxxxxxxxxxxx> wrote:
>
> Hi Dmitry,
>
> you want me to use this generic power domain index ?
> => RPMPD_VDDCX

Which indices are used by the rest of the file?

Also, please , stop top-posting. And don't post HTML emails.

> On 6/28/2026 6:05 PM, Dmitry Baryshkov wrote:
> > On Sat, Jun 27, 2026 at 03:31:35PM +0530, Nabige Aala wrote:
> >> Add the SoC-level display subsystem nodes for Shikra: MDSS wrapper,
> >> DPU display controller, DSI host controller, and 14nm DSI PHY.
> >>
> >> Shikra uses DPU 6.5 hardware (same as QCM2290). Platform-specific
> >> compatible strings are used as the primary match with QCM2290 fallbacks
> >> to reuse the existing driver support.
> >>
> >> The dispcc clock inputs for the DSI byte and pixel PLLs are wired
> >> from mdss_dsi0_phy.
> >>
> >> Signed-off-by: Nabige Aala <nabige.aala@xxxxxxxxxxxxxxxx>
> >> ---
> >>   arch/arm64/boot/dts/qcom/shikra.dtsi | 203 ++++++++++++++++++++++++++++++++++-
> >>   1 file changed, 201 insertions(+), 2 deletions(-)
> >>
> >> +
> >> +                            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> >> +                                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
> >> +                                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
> >> +                                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> >> +                                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> >> +                            clock-names = "bus",
> >> +                                          "iface",
> >> +                                          "core",
> >> +                                          "lut",
> >> +                                          "vsync";
> >> +
> >> +                            operating-points-v2 = <&mdp_opp_table>;
> >> +                            power-domains = <&rpmpd QCM2290_VDDCX>;
> > Don't blindly copy bits and pieces from other platforms. No, its' not
> > QCM2290.
> >
> >> +
> >> +                            ports {
> >> +                                    #address-cells = <1>;
> >> +                                    #size-cells = <0>;
> >> +
> > [...]
> >
> >> +
> >> +                            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> >> +                                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> >> +                            assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
> >> +                                                     <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
> >> +
> >> +                            operating-points-v2 = <&dsi_opp_table>;
> >> +                            power-domains = <&rpmpd QCM2290_VDDCX>;
> > The same.
> >
> >> +                            phys = <&mdss_dsi0_phy>;
> >> +
> >> +                            #address-cells = <1>;
> >> +                            #size-cells = <0>;
> >> +
> >> +                            status = "disabled";
> >> +



-- 
With best wishes
Dmitry