Re: [PATCH 2/5] arm64: dts: qcom: shikra-cqm-evk: Enable display and add ili7807s panel
From: Arpit Saini
Date: Mon Jun 29 2026 - 06:54:59 EST
Hi Dmitry,
On 6/28/2026 6:00 PM, Dmitry Baryshkov wrote:
On Sat, Jun 27, 2026 at 03:31:36PM +0530, Nabige Aala wrote:
From: Arpit Saini <arpit.saini@xxxxxxxxxxxxxxxx>Empty lines before the status property, please.
Enable the Shikra MDSS display subsystem on the Shikra CQM EVK
board and add the DLC0697 MIPI DSI display panel node.
Pin pm4125_l5 to 1.232V with regulator-allow-set-load
for DSI PHY PLL stability.
Signed-off-by: Arpit Saini <arpit.saini@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 104 ++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 683b5245923b..c9ea093cd8ca 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,18 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ lcd_bias: regulator-lcd-bias {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_bias";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&pm4125_l17>;
+ gpio = <&tlmm 151 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-0 = <&lcd_bias_en>;
+ pinctrl-names = "default";
+ };
+
wcn3988-pmu {
compatible = "qcom,wcn3988-pmu";
@@ -60,6 +72,52 @@ vreg_pmu_ch1: ldo4 {
};
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm4125_l5>;
+ status = "okay";
Ack, will update.
+AVEE is typically the negative / ground supply. How can it be supplied
+ panel@0 {
+ compatible = "dlc,dlc0697", "ilitek,ili7807s";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+
+ vddi-supply = <&pm4125_l15>;
+ avdd-supply = <&lcd_bias>;
+ avee-supply = <&lcd_bias>;
by the same regulator as AVDD?
Ack , I will update this using two seperate regulator-fixed nodes, vreg_disp_p and vreg_disp_n
as defined in schematics.
Thanks for pointing out.
+I think, recent recommendation is to sort these entries by the pin
+ pinctrl-0 = <&panel_bl_en &panel_rst_n &panel_te_pin>;
+ pinctrl-1 = <&panel_bl_en_suspend &panel_rst_n_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
+&pm4125_l5 {
+ /* DSI VDDA - must be at NOM voltage for PHY PLL lock */
+ regulator-min-microvolt = <1232000>;
+ regulator-max-microvolt = <1232000>;
+ regulator-allow-set-load;
+};
+
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
@@ -116,3 +174,49 @@ &wifi {
status = "okay";
};
+
+&tlmm {
+ lcd_bias_en: lcd-bias-en-state {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ panel_bl_en: panel-bl-en-state {
+ pins = "gpio91";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
number.
Ack, will update.
+ };
+
+ panel_bl_en_suspend: panel-bl-en-suspend-state {
+ pins = "gpio91";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+
+ panel_rst_n: panel-rst-n-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ panel_rst_n_suspend: panel-rst-n-suspend-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ panel_te_pin: panel-te-pin-state {
+ pins = "gpio86";
+ function = "mdp_vsync_p";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
--
2.34.1