[PATCH v3 10/13] ARM: dts: microchip: sama7d65: add otpc node
From: Varshini Rajendran
Date: Tue Jun 30 2026 - 05:48:35 EST
Add OTPC node along with temperature calibration cell.
Signed-off-by: Varshini Rajendran <varshini.rajendran@xxxxxxxxxxxxx>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index ba775459a816..5867fda378b1 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/at91-usart.h>
+#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
/ {
model = "Microchip SAMA7D65 family SoC";
@@ -1112,6 +1113,21 @@ ddr3phy: ddr3phy@e3804000 {
reg = <0xe3804000 0x1000>;
};
+ otpc: efuse@e8c00000 {
+ compatible = "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "syscon";
+ reg = <0xe8c00000 0x100>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ temperature_calib: calib@41435354 {
+ reg = <0x41435354 0x2c>; /* Temp calib data packet TAG */
+ };
+ };
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,cortex-a7-gic";
reg = <0xe8c11000 0x1000>,
--
2.34.1