[BOF]arm: resctrl: L3 cache partitioning via CLUSTERPARTCR

[Aiqun(Maria) Yu]

Hi all,

L3 cache partitioning is an important feature for improving performance
isolation of latency-sensitive tasks. While ARM MPAM provides a
comprehensive solution, there exists another ARM register, CLUSTERPARTCR,
which offers L3 cache partitioning functionality similar to MPAM's CPBM
(Cache Portion BitMask) but is not part of the MPAM architecture.

CLUSTERPARTCR is a cluster-level register that allows software to partition
L3 cache capacity among different workloads. Although its partitioning
granularity and flexibility are more limited compared to full MPAM support,
it remains a practically important interface for platforms that do not
implement MPAM but still need L3 cache partitioning capability.

This raises the following questions for the community:

  1. Is there interest in accommodating CLUSTERPARTCR-based L3 partitioning
     within the existing resctrl framework, given that it provides similar
     semantics to Intel RDT's cache allocation technology (CAT)?

  2. Alternatively, would it be more appropriate to integrate it under the
     MPAM resctrl framework as a non-MPAM backend, given the functional
     similarity to MPAM CPBM?

  3. Are there any concerns or constraints in the current resctrl/MPAM
     framework that would prevent such an integration?

Any comments, suggestions, or pointers to prior discussion on this topic
are very much appreciated.

More references:
==========
Reference to [1], and more detailed information like below:
the CLUSTERPARTCR_EL1 to 0x00008601 to configure these three L3 cache
partitions:
• Scheme ID 0 (1/4 of the cache).
• Scheme ID 2 (1/2 of the cache).
• Scheme ID 3 (1/4 of the cache).


The OS, running at EL1, can set the CLUSTERTHREADSID_EL1 to 0x0 or 0x1
to select between the two L3 cache partitions allocated to it. These
would be mapped to scheme IDs 2 and 3 by the CLUSTERTHREADSIDOVR_EL1
register. The OS can update this register on context switches to select
which partition each process has access to.

[1]
https://developer.arm.com/documentation/100453/0401/L3-cache/L3-cache-partitioning?lang=en
-- 
Thx and BRs,
Aiqun(Maria) Yu