RE: [PATCH v18 1/4] pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L

[Biju Das]

Hi Linus Walleij,

> -----Original Message-----
> From: Linus Walleij <linusw@xxxxxxxxxx>
> Sent: 30 June 2026 14:29
> Subject: Re: [PATCH v18 1/4] pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L
> 
> Hi Biju,
> 
> thanks for your patch!
> 
> On Mon, Jun 22, 2026 at 5:48 PM Biju <biju.das.au@xxxxxxxxx> wrote:
> 
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Add power-on control (POC) support for SD channels 1 and 2 on the
> > RZ/G3L SoC (r9a08g046).
> >
> > Introduce PIN_CFG_IO_VMC_SD2 capability flag (bit 22) and SD_CH2_POC
> > register offset (0x3024). Extend rzg2l_caps_to_pwr_reg() to return
> > SD_CH2_POC when PIN_CFG_IO_VMC_SD2 is set.
> >
> > Replace RZG3L_MPXED_PIN_FUNCS() with RZG2L_MPXED_COMMON_PIN_FUNCS()
> > for port PG and PH pins, dropping PIN_CFG_SOFT_PS which is
> > inappropriate for SD pins, and annotate them with PIN_CFG_IO_VMC_SD1
> > and PIN_CFG_IO_VMC_SD2 respectively.
> >
> > Annotate all RZ/G3L SD0 dedicated pins (CLK, CMD, RST#, DS, DAT0–DAT7)
> > with PIN_CFG_IO_VMC_SD0 so that power-source register lookups work
> > correctly for those pins.
> >
> > Add sd_ch2 field to rzg2l_register_offsets and rzg2l_pinctrl_reg_cache
> > to save and restore the SD_CH2_POC register across suspend/resume cycles.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Is this patch Geert can apply separately for pin control in the end?

Yes, Geert will apply this patch to renesas-pinctrl tree and
then pull request to you.

Cheers,
Biju