linux-next: manual merge of the drm-intel tree with the origin tree

[Mark Brown]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/display/intel_cdclk.c

between commit:

  2ee8dbd880b14 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")

from the origin tree and commits:

  3f9de66f8acbf ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")
  795e90164a3b8 ("drm/i915/cdclk: Print the reason for the CDCLK sanitization")
  67d77d9472c66 ("drm/i915/cdclk: Introduce bxt_cdclk_cd2x_pipe_mask() and use it")
  8984b402e02ff ("drm/i915/cdclk: Use the TGL+ CD2x pipe select bits also on ICL")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --combined drivers/gpu/drm/i915/display/intel_cdclk.c
index 7bc9b956554ba,d3c5e3438d192..0000000000000
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@@ -1229,23 -1229,28 +1229,28 @@@ static void skl_set_cdclk(struct intel_
  
  static void skl_sanitize_cdclk(struct intel_display *display)
  {
- 	u32 cdctl, expected;
+ 	u32 cdctl, expected, swf18;
  
  	/*
  	 * check if the pre-os initialized the display
  	 * There is SWF18 scratchpad register defined which is set by the
  	 * pre-os which can be used by the OS drivers to check the status
  	 */
- 	if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
+ 	swf18 = intel_de_read(display, SWF_ILK(0x18));
+ 	if ((swf18 & 0x00FFFFFF) == 0) {
+ 		drm_dbg_kms(display->drm, "Sanitizing CDCLK due to SWF18 0x%x\n", swf18);
  		goto sanitize;
+ 	}
  
  	intel_update_cdclk(display);
  	intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
  
  	/* Is PLL enabled and locked ? */
  	if (display->cdclk.hw.vco == 0 ||
- 	    display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
+ 	    display->cdclk.hw.cdclk == display->cdclk.hw.bypass) {
+ 		drm_dbg_kms(display->drm, "Sanitizing CDCLK due to PLL not enabled/locked\n");
  		goto sanitize;
+ 	}
  
  	/* DPLL okay; verify the cdclock
  	 *
@@@ -1261,8 -1266,11 +1266,11 @@@
  		cdctl &= ~CDCLK_FREQ_DECIMAL_MASK;
  		cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK;
  
- 		if (cdctl != expected)
+ 		if (cdctl != expected) {
+ 			drm_dbg_kms(display->drm, "Sanitizing CDCLK due to CDCLK_CTL 0x%x, expected 0x%x)\n",
+ 				    intel_de_read(display, CDCLK_CTL), expected);
  			goto sanitize;
+ 		}
  
  		drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n",
  			    intel_de_read(display, CDCLK_CTL), expected);
@@@ -1274,8 -1282,6 +1282,6 @@@
  	return;
  
  sanitize:
- 	drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
- 
  	/* force cdclk programming */
  	display->cdclk.hw.cdclk = 0;
  	/* force full PLL disable + enable */
@@@ -1938,14 -1944,17 +1944,17 @@@ static void adlp_cdclk_pll_crawl(struc
  	display->cdclk.hw.vco = vco;
  }
  
+ static u32 bxt_cdclk_cd2x_pipe_mask(struct intel_display *display)
+ {
+ 	if (DISPLAY_VER(display) >= 11)
+ 		return ICL_CDCLK_CD2X_PIPE_MASK;
+ 	else
+ 		return BXT_CDCLK_CD2X_PIPE_MASK;
+ }
+ 
  static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
  {
- 	if (DISPLAY_VER(display) >= 12) {
- 		if (pipe == INVALID_PIPE)
- 			return TGL_CDCLK_CD2X_PIPE_NONE;
- 		else
- 			return TGL_CDCLK_CD2X_PIPE(pipe);
- 	} else if (DISPLAY_VER(display) >= 11) {
+ 	if (DISPLAY_VER(display) >= 11) {
  		if (pipe == INVALID_PIPE)
  			return ICL_CDCLK_CD2X_PIPE_NONE;
  		else
@@@ -2340,18 -2349,24 +2349,24 @@@ static void bxt_sanitize_cdclk(struct i
  	intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
  
  	if (display->cdclk.hw.vco == 0 ||
- 	    display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
+ 	    display->cdclk.hw.cdclk == display->cdclk.hw.bypass) {
+ 		drm_dbg_kms(display->drm, "Sanitizing CDCLK due to PLL not enabled/locked\n");
  		goto sanitize;
+ 	}
  
  	/* Make sure this is a legal cdclk value for the platform */
  	cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
- 	if (cdclk != display->cdclk.hw.cdclk)
+ 	if (cdclk != display->cdclk.hw.cdclk) {
+ 		drm_dbg_kms(display->drm, "Sanitizing CDCLK due to bad CDCLK frequency\n");
  		goto sanitize;
+ 	}
  
  	/* Make sure the VCO is correct for the cdclk */
  	vco = bxt_calc_cdclk_pll_vco(display, cdclk);
- 	if (vco != display->cdclk.hw.vco)
+ 	if (vco != display->cdclk.hw.vco) {
+ 		drm_dbg_kms(display->drm, "Sanitizing CDCLK due to bad VCO frequency\n");
  		goto sanitize;
+ 	}
  
  	/*
  	 * Some BIOS versions leave an incorrect decimal frequency value and
@@@ -2366,7 -2381,7 +2381,7 @@@
  	 * dividers both syncing to an active pipe, or asynchronously
  	 * (PIPE_NONE).
  	 */
- 	cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
+ 	cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
  	cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
  
  	if (cdctl != expected) {
@@@ -2375,8 -2390,11 +2390,11 @@@
  			cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK;
  		}
  
- 		if (cdctl != expected)
+ 		if (cdctl != expected) {
+ 			drm_dbg_kms(display->drm, "Sanitizing CDCLK due to CDCLK_CTL 0x%x, expected 0x%x\n",
+ 				    intel_de_read(display, CDCLK_CTL), expected);
  			goto sanitize;
+ 		}
  
  		drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n",
  			    intel_de_read(display, CDCLK_CTL), expected);
@@@ -2388,8 -2406,6 +2406,6 @@@
  	return;
  
  sanitize:
- 	drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
- 
  	/* force cdclk programming */
  	display->cdclk.hw.cdclk = 0;

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