[PATCH] arm64: dts: qcom: Rename pci@ nodes to pcie@
From: Konrad Dybcio
Date: Wed Jul 01 2026 - 06:34:29 EST
From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
PCIe hosts/devices commonly use the 'pcie' for their node name to
reflect they're not legacy PCI.
Every couple months someone comes around to clean this up because
people keep introducing new uses of 'pci@'. Seems like it's my turn
now, so do that for RCs and the downstream devices (switches etc.)
defined in board files.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/hamoa.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso | 4 ++--
arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 4 ++--
arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso | 4 ++--
arch/arm64/boot/dts/qcom/monaco.dtsi | 4 ++--
.../arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 8 ++++----
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++--
9 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 20b49af7298e..4a2be27601a0 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2750,7 +2750,7 @@ pcie_west_slv_noc: interconnect@1920000 {
#interconnect-cells = <2>;
};
- pcie4: pci@1bf0000 {
+ pcie4: pcie@1bf0000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01bf0000 0x0 0x3000>,
@@ -2960,7 +2960,7 @@ pcie4_phy: phy@1bf6000 {
status = "disabled";
};
- pcie5: pci@1b40000 {
+ pcie5: pcie@1b40000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01b40000 0x0 0x3000>,
@@ -3226,7 +3226,7 @@ pcie5_phy: phy@1b50000 {
status = "disabled";
};
- pcie6: pci@1c00000 {
+ pcie6: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01c00000 0x0 0x3000>,
@@ -3436,7 +3436,7 @@ pcie6_phy: phy@1c06000 {
status = "disabled";
};
- pcie3b: pci@1b80000 {
+ pcie3b: pcie@1b80000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01b80000 0x0 0x3000>,
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 4ba751a65142..56cfce354eb9 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -3462,7 +3462,7 @@ pcie3_phy: phy@1be0000 {
status = "disabled";
};
- pcie6a: pci@1bf8000 {
+ pcie6a: pcie@1bf8000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
reg = <0 0x01bf8000 0 0x3000>,
@@ -3605,7 +3605,7 @@ pcie6a_phy: phy@1bfc000 {
status = "disabled";
};
- pcie5: pci@1c00000 {
+ pcie5: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
reg = <0 0x01c00000 0 0x3000>,
@@ -3742,7 +3742,7 @@ pcie5_phy: phy@1c06000 {
status = "disabled";
};
- pcie4: pci@1c08000 {
+ pcie4: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
reg = <0 0x01c08000 0 0x3000>,
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
index 44bd9b1a1765..4fc5f482a18f 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
@@ -271,7 +271,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
- pci@0,0 {
+ pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -279,7 +279,7 @@ pci@0,0 {
ranges;
};
- pci@0,1 {
+ pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts
index 379b796f261f..e1cc3954efe8 100644
--- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts
@@ -340,7 +340,7 @@ &pcie1 {
&pcieport0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- pci@0,0 {
+ pcie@0,0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -348,7 +348,7 @@ pci@0,0 {
ranges;
reg = <0x010000 0x00 0x00 0x00 0x00>;
- pci@2,0 {
+ pcie@2,0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
index e6beb4393430..77c28c19d17a 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
@@ -117,7 +117,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
- pci@0,0 {
+ pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -125,7 +125,7 @@ pci@0,0 {
ranges;
};
- pci@0,1 {
+ pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index e4c8466f941b..c354fb4ce1fe 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2276,7 +2276,7 @@ mmss_noc: interconnect@17a0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
reg = <0x0 0x01c00000 0x0 0x3000>,
@@ -2455,7 +2455,7 @@ pcie0_phy: phy@1c04000 {
status = "disabled";
};
- pcie1: pci@1c10000 {
+ pcie1: pcie@1c10000 {
device_type = "pci";
compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
reg = <0x0 0x01c10000 0x0 0x3000>,
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 83908db335af..937b63eae3ba 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -130,7 +130,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
- pci@0,0 {
+ pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -138,7 +138,7 @@ pci@0,0 {
ranges;
};
- pci@0,1 {
+ pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -225,7 +225,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
- pci@0,0 {
+ pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -233,7 +233,7 @@ pci@0,0 {
ranges;
};
- pci@0,1 {
+ pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 37a3b51323ce..8dde7f4b2dc6 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -954,7 +954,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
- pci@0,0 {
+ pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -962,7 +962,7 @@ pci@0,0 {
ranges;
};
- pci@0,1 {
+ pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
index a5ad796cb65d..7827f66342c9 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
@@ -784,7 +784,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
- pci@0,0 {
+ pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -792,7 +792,7 @@ pci@0,0 {
ranges;
};
- pci@0,1 {
+ pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
---
base-commit: 7de6ae9e12207ec146f2f3f1e58d1a99317e88bc
change-id: 20260701-topic-dts_pci_pcie-f2fb8534fc39
Best regards,
--
Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>