[PATCH 1/4] dt-bindings: clock: qcom: Add video clock controller on Nord SoC
From: Taniya Das
Date: Mon Jul 06 2026 - 05:24:24 EST
Add compatible string for Nord video clock controller and the bindings
for Nord Qualcomm SoC.
Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
---
.../bindings/clock/qcom,sm8450-videocc.yaml | 2 ++
include/dt-bindings/clock/qcom,nord-videocc.h | 40 ++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
index 5d77029bfaf8830e2bc0c3b8f323c818ee48dba2..9b9878e9b9cfc669e9b5f1c42a68e9e0c11eebd3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
@@ -17,6 +17,7 @@ description: |
See also:
include/dt-bindings/clock/qcom,glymur-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
+ include/dt-bindings/clock/qcom,nord-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
@@ -27,6 +28,7 @@ properties:
enum:
- qcom,glymur-videocc
- qcom,kaanapali-videocc
+ - qcom,nord-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc
diff --git a/include/dt-bindings/clock/qcom,nord-videocc.h b/include/dt-bindings/clock/qcom,nord-videocc.h
new file mode 100644
index 0000000000000000000000000000000000000000..8d75460211099f3b2463c5c544ce3e85155c6466
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-videocc.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_NORD_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK_SRC 0
+#define VIDEO_CC_MVS0_CLK 1
+#define VIDEO_CC_MVS0_CLK_SRC 2
+#define VIDEO_CC_MVS0_DIV_CLK_SRC 3
+#define VIDEO_CC_MVS0_FREERUN_CLK 4
+#define VIDEO_CC_MVS0_SHIFT_CLK 5
+#define VIDEO_CC_MVS0C_CLK 6
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7
+#define VIDEO_CC_MVS0C_FREERUN_CLK 8
+#define VIDEO_CC_MVS0C_SHIFT_CLK 9
+#define VIDEO_CC_MVS1_CLK 10
+#define VIDEO_CC_MVS1_DIV_CLK_SRC 11
+#define VIDEO_CC_MVS1_FREERUN_CLK 12
+#define VIDEO_CC_MVS1_SHIFT_CLK 13
+#define VIDEO_CC_PLL0 14
+#define VIDEO_CC_SLEEP_CLK_SRC 15
+#define VIDEO_CC_XO_CLK_SRC 16
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0_GDSC 0
+#define VIDEO_CC_MVS0C_GDSC 1
+#define VIDEO_CC_MVS1_GDSC 2
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR 0
+#define VIDEO_CC_MVS0_BCR 1
+#define VIDEO_CC_MVS0C_CLK_ARES 2
+#define VIDEO_CC_MVS0C_BCR 3
+#define VIDEO_CC_MVS1_BCR 4
+
+#endif
--
2.34.1