Re: [PATCH v7 5/7] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support

[Qiang Yu]

On Mon, Jul 06, 2026 at 02:47:40PM +0200, Konrad Dybcio wrote:
> On 7/2/26 9:36 AM, Qiang Yu wrote:
> > Mahua is based on Glymur but uses a different QREF topology, requiring
> > distinct regulator lists and clock descriptors for its PCIe clock
> > references.
> > 
> > Add mahua-specific regulator arrays and clk descriptor table, and use
> > match_data to select the correct descriptor table per compatible string at
> > probe time.
> > 
> > Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> > ---
> 
> [...]
> 
> > +static const struct qcom_clk_ref_desc * const tcsr_cc_mahua_clk_descs[] = {
> > +	[TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> OK
> 
> > +		.name = "tcsr_edp_clkref_en",
> > +		.offset = 0x60,
> > +		.regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators),
> > +	},
> > +	[TCSR_PCIE_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> (PCIe4) OK
> 
> > +		.name = "tcsr_pcie_2_clkref_en",
> > +		.offset = 0x4c,
> > +		.regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),
> > +	},
> > +	[TCSR_PCIE_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> (PCIe3) OK
> 
> > +		.name = "tcsr_pcie_3_clkref_en",
> > +		.offset = 0x54,
> > +		.regulator_names = mahua_tcsr_tx1_rpt012_rx2_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators),
> > +	},
> > +	[TCSR_PCIE_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> [!] (PCIe6) This needs +RPT2 +RX2 -RX1

Correct, will fix it in v8. I thought PCIe4 PHY and PCIe6 PHY use same
QREF.

- Qiang Yu
> 
> > +		.name = "tcsr_pcie_4_clkref_en",
> > +		.offset = 0x58,
> > +		.regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),
> > +	},
> > +	[TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> (USB_HS) OK
> 
> > +		.name = "tcsr_usb2_1_clkref_en",
> > +		.offset = 0x6c,
> > +		.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
> > +	},
> > +	[TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> (MP0_HS) OK
> 
> > +		.name = "tcsr_usb2_2_clkref_en",
> > +		.offset = 0x70,
> > +		.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
> > +	},
> > +	[TCSR_USB2_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> (MP1_HS) OK
> 
> > +		.name = "tcsr_usb2_3_clkref_en",
> > +		.offset = 0x74,
> > +		.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
> > +	},
> > +	[TCSR_USB2_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> ("USB2_2") OK> +		.name = "tcsr_usb2_4_clkref_en",
> > +		.offset = 0x88,
> > +		.regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators),
> > +	},
> > +	[TCSR_USB3_0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> (MP0_SS) OK> +		.name = "tcsr_usb3_0_clkref_en",
> > +		.offset = 0x64,
> > +		.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
> > +	},
> > +	[TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> (MP1_SS) OK
> 
> > +		.name = "tcsr_usb3_1_clkref_en",
> > +		.offset = 0x68,
> > +		.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
> > +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
> > +	},
> > +	[TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> OK
> 
> > +		.name = "tcsr_usb4_1_clkref_en",
> > +		.offset = 0x44,
> > +	},
> > +	[TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> 
> OK
> 
> Konrad