[PATCH v9 2/2] arm64: dts: qcom: monaco: enable inline crypto engine for SDHC
From: Kuldeep Singh
Date: Tue Jul 07 2026 - 03:17:36 EST
From: Neeraj Soni <neeraj.soni@xxxxxxxxxxxxxxxx>
Add the dedicated ICE node for monaco and reference it from the SDHC
controller via qcom,ice.
Also, define power-domains and clocks properties similar to the UFS
node.
Signed-off-by: Neeraj Soni <neeraj.soni@xxxxxxxxxxxxxxxx>
Co-developed-by: Kuldeep Singh <kuldeep.singh@xxxxxxxxxxxxxxxx>
Signed-off-by: Kuldeep Singh <kuldeep.singh@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 400c75437978..ffb13d61ee36 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -4864,6 +4864,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
supports-cqe;
dma-coherent;
+ qcom,ice = <&sdhc_ice>;
+
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
@@ -4896,6 +4898,17 @@ opp-384000000 {
};
};
+ sdhc_ice: crypto@87c8000 {
+ compatible = "qcom,qcs8300-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x087c8000 0x0 0x18000>;
+ clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
+ clock-names = "core",
+ "iface";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ };
+
usb_1_hsphy: phy@8904000 {
compatible = "qcom,qcs8300-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
--
2.34.1