RE: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC

[Biju Das]

Hi Wolfram,

> -----Original Message-----
> From: Biju Das
> Sent: 17 June 2026 13:43
> Subject: RE: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
> 
> Hi Wolfram,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> > Sent: 17 June 2026 13:20
> > Subject: Re: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi:
> > Document RZ/G3L (r9a08g046) SoC
> >
> > Hi Biju,
> >
> > On Wed, Jun 03, 2026 at 07:57:01AM +0100, Biju wrote:
> > > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > >
> > > Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI
> > > controller is similar to RZ/G2L but has five clocks (core, clkh, cd,
> > > aclk, aclkm) and three resets (rst, axim, axis), so update the
> > > clocks/clock-names maximum to 5 and resets/reset-names maximum to 3.
> > > It has an internal divider for all modes except HS400, and a
> > > 2048-bit divider compared to 512 on others.
> > >
> > > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > I know you work on v18 already, but some high level remarks already.
> 
> OK.
> 
> >
> > > +              - description: ACLK/IACLKS, SDHI channel bus clock.
> > > +              - description: IACLKM, SDHI channel bus clock m.
> >
> > What does 's' and 'm' stand for? Is it mentioned in the docs? Would be nice to have here as well, if
> so.
> 
> >
> > > +          resets:
> > > +            items:
> > > +              - description: rst, Core reset.
> > > +              - description: axim, SDHI axi bus reset m.
> > > +              - description: axis, SDHI axi bus reset s.
> >
> > Ditto.
> 
> The reset signal mentioned in the hardware manual are SDHIx_IXRST, SDHIx_IXRSTAXIM and SDHIx_IXRSTAXIS
> (where x=0,1,2)
> 
> I will check this as well with hardware/documentation team and update you.

I got feedback from hardware team

These clocks and reset signals are intended for the AXI Master and AXI Slave
interfaces.

Do you agree free the below description? please let me know.

              - description: ACLK/IACLKM, SDHI channel bus clock/ AXI master bus clock.
              - description: IACLKS, SDHI channel AXI slave bus clock.
          clock-names:
            items:
              - const: core
              - const: clkh
              - const: cd
              - const: aclkm
              - const: aclks
          resets:
            items:
              - description: rst, Core reset.
              - description: axim, SDHI AXI master bus reset.
              - description: axis, SDHI AXI slave bus reset.

Cheers,
Biju