[PATCH 3/4] serial: 8250: map UAPI port type to internal enum

From: Christian Marangi

Date: Thu Jul 09 2026 - 17:05:34 EST

There is currently some confusion when a new 8250 UART device needs to be
defined with the related index for uart_config[] to be directly defined in
UAPI header.

There isn't any specific reason to define the index directly in UAPI header
unless it's also needed to be defined for userspace usage.

To try to address this confusion and making it clear how these specific
index should be defined and where, create a dedicated enum in 8250.h
with all the current defined values in UAPI header and document how these
id should be defined.

Rename the define in 8250_port.c with the new UART_ prefix.

Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
---
drivers/tty/serial/8250/8250.h | 122 ++++++++++++++++++++++++++++
drivers/tty/serial/8250/8250_port.c | 72 ++++++++--------
2 files changed, 158 insertions(+), 36 deletions(-)

diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
index 77fe0588fd6b..3a45f957d3a9 100644
--- a/drivers/tty/serial/8250/8250.h
+++ b/drivers/tty/serial/8250/8250.h
@@ -73,6 +73,128 @@ struct serial8250_config {
unsigned int flags;
};

+/*
+ * The uart_config[] array index is referenced and defined from index
+ * in uapi/linux/serial.h and uapi/linux/serial_core.h.
+ *
+ * This was old practice and for anything that doesn't need to support
+ * userspace, new type should be limited and added only HERE.
+ *
+ * Any UART port that requires userspace support, should define the
+ * dedicated index in the UAPI header and reference it when added
+ * to this enum table.
+ */
+enum uart_port_type {
+ /* From uapi/linux/serial.h */
+ UART_PORT_UNKNOWN = PORT_UNKNOWN, /* 0 */
+ UART_PORT_8250 = PORT_8250,
+ UART_PORT_16450 = PORT_16450,
+ UART_PORT_16550 = PORT_16550,
+ UART_PORT_16550A = PORT_16550A,
+ UART_PORT_CIRRUS = PORT_CIRRUS,
+ UART_PORT_16650 = PORT_16650,
+ UART_PORT_16650V2 = PORT_16650V2,
+ UART_PORT_16750 = PORT_16750,
+ UART_PORT_STARTECH = PORT_STARTECH,
+ UART_PORT_16C950 = PORT_16C950,
+ UART_PORT_16654 = PORT_16654,
+ UART_PORT_16850 = PORT_16850,
+ UART_PORT_RSA = PORT_RSA, /* 13 */
+
+ /* From uapi/linux/serial_core.h (14-123) */
+ UART_PORT_NS16550A = PORT_NS16550A, /* 14 */
+ UART_PORT_XSCALE = PORT_XSCALE,
+ UART_PORT_RM9000 = PORT_RM9000,
+ UART_PORT_OCTEON = PORT_OCTEON,
+ UART_PORT_AR7 = PORT_AR7,
+ UART_PORT_U6_16550A = PORT_U6_16550A,
+ UART_PORT_TEGRA = PORT_TEGRA,
+ UART_PORT_XR17D15X = PORT_XR17D15X,
+ UART_PORT_LPC3220 = PORT_LPC3220,
+ UART_PORT_8250_CIR = PORT_8250_CIR,
+ UART_PORT_XR17V35X = PORT_XR17V35X,
+ UART_PORT_BRCM_TRUMANAGE = PORT_BRCM_TRUMANAGE,
+ UART_PORT_ALTR_16550_F32 = PORT_ALTR_16550_F32,
+ UART_PORT_ALTR_16550_F64 = PORT_ALTR_16550_F64,
+ UART_PORT_ALTR_16550_F128 = PORT_ALTR_16550_F128,
+ UART_PORT_RT2880 = PORT_RT2880,
+ UART_PORT_16550A_FSL64 = PORT_16550A_FSL64,
+ UART_PORT_PXA = PORT_PXA,
+ UART_PORT_AMBA = PORT_AMBA,
+ UART_PORT_CLPS711X = PORT_CLPS711X,
+ UART_PORT_SA1100 = PORT_SA1100,
+ UART_PORT_UART00 = PORT_UART00,
+ UART_PORT_OWL = PORT_OWL,
+ UART_PORT_21285 = PORT_21285,
+ UART_PORT_SUNZILOG = PORT_SUNZILOG,
+ UART_PORT_SUNSAB = PORT_SUNSAB,
+ UART_PORT_NPCM = PORT_NPCM,
+ UART_PORT_TEGRA_TCU = PORT_TEGRA_TCU,
+ UART_PORT_ASPEED_VUART = PORT_ASPEED_VUART,
+ UART_PORT_PCH_8LINE = PORT_PCH_8LINE,
+ UART_PORT_PCH_2LINE = PORT_PCH_2LINE,
+ UART_PORT_DZ = PORT_DZ,
+ UART_PORT_ZS = PORT_ZS,
+ UART_PORT_MUX = PORT_MUX,
+ UART_PORT_ATMEL = PORT_ATMEL,
+ UART_PORT_MAC_ZILOG = PORT_MAC_ZILOG,
+ UART_PORT_PMAC_ZILOG = PORT_PMAC_ZILOG,
+ UART_PORT_SCI = PORT_SCI,
+ UART_PORT_SCIF = PORT_SCIF,
+ UART_PORT_IRDA = PORT_IRDA,
+ UART_PORT_IP22ZILOG = PORT_IP22ZILOG,
+ UART_PORT_CPM = PORT_CPM,
+ UART_PORT_MPC52xx = PORT_MPC52xx,
+ UART_PORT_ICOM = PORT_ICOM,
+ UART_PORT_IMX = PORT_IMX,
+ UART_PORT_TXX9 = PORT_TXX9,
+ UART_PORT_JSM = PORT_JSM,
+ UART_PORT_SUNHV = PORT_SUNHV,
+ UART_PORT_UARTLITE = PORT_UARTLITE,
+ UART_PORT_BCM7271 = PORT_BCM7271,
+ UART_PORT_SB1250_DUART = PORT_SB1250_DUART,
+ UART_PORT_MCF = PORT_MCF,
+ UART_PORT_SC26XX = PORT_SC26XX,
+ UART_PORT_SCIFA = PORT_SCIFA,
+ UART_PORT_S3C6400 = PORT_S3C6400,
+ UART_PORT_MAX3100 = PORT_MAX3100,
+ UART_PORT_TIMBUART = PORT_TIMBUART,
+ UART_PORT_MSM = PORT_MSM,
+ UART_PORT_BCM63XX = PORT_BCM63XX,
+ UART_PORT_APBUART = PORT_APBUART,
+ UART_PORT_ALTERA_JTAGUART = PORT_ALTERA_JTAGUART,
+ UART_PORT_ALTERA_UART = PORT_ALTERA_UART,
+ UART_PORT_SCIFB = PORT_SCIFB,
+ UART_PORT_MAX310X = PORT_MAX310X,
+ UART_PORT_DA830 = PORT_DA830,
+ UART_PORT_OMAP = PORT_OMAP,
+ UART_PORT_VT8500 = PORT_VT8500,
+ UART_PORT_XUARTPS = PORT_XUARTPS,
+ UART_PORT_AR933X = PORT_AR933X,
+ UART_PORT_MCHP16550A = PORT_MCHP16550A,
+ UART_PORT_ARC = PORT_ARC,
+ UART_PORT_RP2 = PORT_RP2,
+ UART_PORT_LPUART = PORT_LPUART,
+ UART_PORT_HSCIF = PORT_HSCIF,
+ UART_PORT_ASC = PORT_ASC,
+ UART_PORT_MEN_Z135 = PORT_MEN_Z135,
+ UART_PORT_SC16IS7XX = PORT_SC16IS7XX,
+ UART_PORT_MESON = PORT_MESON,
+ UART_PORT_DIGICOLOR = PORT_DIGICOLOR,
+ UART_PORT_SPRD = PORT_SPRD,
+ UART_PORT_STM32 = PORT_STM32,
+ UART_PORT_MVEBU = PORT_MVEBU,
+ UART_PORT_PIC32 = PORT_PIC32,
+ UART_PORT_MPS2UART = PORT_MPS2UART,
+ UART_PORT_MTK_BTIF = PORT_MTK_BTIF,
+ UART_PORT_RDA = PORT_RDA,
+ UART_PORT_MLB_USIO = PORT_MLB_USIO,
+ UART_PORT_SIFIVE_V0 = PORT_SIFIVE_V0,
+ UART_PORT_SUNIX = PORT_SUNIX,
+ UART_PORT_LINFLEXUART = PORT_LINFLEXUART,
+ UART_PORT_SUNPLUS = PORT_SUNPLUS, /* 123 */
+};
+
#define UART_CAP_FIFO BIT(8) /* UART has FIFO */
#define UART_CAP_EFR BIT(9) /* UART has EFR */
#define UART_CAP_SLEEP BIT(10) /* UART has IER sleep */
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 033d8fb8bb23..a0b80324a559 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -43,27 +43,27 @@
* Here we define the default xmit fifo size used for each type of UART.
*/
static const struct serial8250_config uart_config[] = {
- [PORT_UNKNOWN] = {
+ [UART_PORT_UNKNOWN] = {
.name = "unknown",
.fifo_size = 1,
.tx_loadsz = 1,
},
- [PORT_8250] = {
+ [UART_PORT_8250] = {
.name = "8250",
.fifo_size = 1,
.tx_loadsz = 1,
},
- [PORT_16450] = {
+ [UART_PORT_16450] = {
.name = "16450",
.fifo_size = 1,
.tx_loadsz = 1,
},
- [PORT_16550] = {
+ [UART_PORT_16550] = {
.name = "16550",
.fifo_size = 1,
.tx_loadsz = 1,
},
- [PORT_16550A] = {
+ [UART_PORT_16550A] = {
.name = "16550A",
.fifo_size = 16,
.tx_loadsz = 16,
@@ -71,18 +71,18 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
- [PORT_CIRRUS] = {
+ [UART_PORT_CIRRUS] = {
.name = "Cirrus",
.fifo_size = 1,
.tx_loadsz = 1,
},
- [PORT_16650] = {
+ [UART_PORT_16650] = {
.name = "ST16650",
.fifo_size = 1,
.tx_loadsz = 1,
.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
},
- [PORT_16650V2] = {
+ [UART_PORT_16650V2] = {
.name = "ST16650V2",
.fifo_size = 32,
.tx_loadsz = 16,
@@ -91,7 +91,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {8, 16, 24, 28},
.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
},
- [PORT_16750] = {
+ [UART_PORT_16750] = {
.name = "TI16750",
.fifo_size = 64,
.tx_loadsz = 64,
@@ -100,12 +100,12 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 16, 32, 56},
.flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
},
- [PORT_STARTECH] = {
+ [UART_PORT_STARTECH] = {
.name = "Startech",
.fifo_size = 1,
.tx_loadsz = 1,
},
- [PORT_16C950] = {
+ [UART_PORT_16C950] = {
.name = "16C950/954",
.fifo_size = 128,
.tx_loadsz = 128,
@@ -114,7 +114,7 @@ static const struct serial8250_config uart_config[] = {
/* UART_CAP_EFR breaks billionon CF bluetooth card. */
.flags = UART_CAP_FIFO | UART_CAP_SLEEP,
},
- [PORT_16654] = {
+ [UART_PORT_16654] = {
.name = "ST16654",
.fifo_size = 64,
.tx_loadsz = 32,
@@ -123,49 +123,49 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {8, 16, 56, 60},
.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
},
- [PORT_16850] = {
+ [UART_PORT_16850] = {
.name = "XR16850",
.fifo_size = 128,
.tx_loadsz = 128,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
},
- [PORT_RSA] = {
+ [UART_PORT_RSA] = {
.name = "RSA",
.fifo_size = 2048,
.tx_loadsz = 2048,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
.flags = UART_CAP_FIFO,
},
- [PORT_NS16550A] = {
+ [UART_PORT_NS16550A] = {
.name = "NS16550A",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_NATSEMI,
},
- [PORT_XSCALE] = {
+ [UART_PORT_XSCALE] = {
.name = "XScale",
.fifo_size = 32,
.tx_loadsz = 32,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
},
- [PORT_OCTEON] = {
+ [UART_PORT_OCTEON] = {
.name = "OCTEON",
.fifo_size = 64,
.tx_loadsz = 64,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO,
},
- [PORT_U6_16550A] = {
+ [UART_PORT_U6_16550A] = {
.name = "U6_16550A",
.fifo_size = 64,
.tx_loadsz = 64,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
- [PORT_TEGRA] = {
+ [UART_PORT_TEGRA] = {
.name = "Tegra",
.fifo_size = 32,
.tx_loadsz = 8,
@@ -174,7 +174,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO | UART_CAP_RTOIE,
},
- [PORT_XR17D15X] = {
+ [UART_PORT_XR17D15X] = {
.name = "XR17D15X",
.fifo_size = 64,
.tx_loadsz = 64,
@@ -182,7 +182,7 @@ static const struct serial8250_config uart_config[] = {
.flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
UART_CAP_SLEEP,
},
- [PORT_XR17V35X] = {
+ [UART_PORT_XR17V35X] = {
.name = "XR17V35X",
.fifo_size = 256,
.tx_loadsz = 256,
@@ -191,7 +191,7 @@ static const struct serial8250_config uart_config[] = {
.flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
UART_CAP_SLEEP,
},
- [PORT_LPC3220] = {
+ [UART_PORT_LPC3220] = {
.name = "LPC3220",
.fifo_size = 64,
.tx_loadsz = 32,
@@ -199,16 +199,16 @@ static const struct serial8250_config uart_config[] = {
UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
.flags = UART_CAP_FIFO,
},
- [PORT_BRCM_TRUMANAGE] = {
+ [UART_PORT_BRCM_TRUMANAGE] = {
.name = "TruManage",
.fifo_size = 1,
.tx_loadsz = 1024,
.flags = UART_CAP_HFIFO,
},
- [PORT_8250_CIR] = {
+ [UART_PORT_8250_CIR] = {
.name = "CIR port"
},
- [PORT_ALTR_16550_F32] = {
+ [UART_PORT_ALTR_16550_F32] = {
.name = "Altera 16550 FIFO32",
.fifo_size = 32,
.tx_loadsz = 32,
@@ -216,7 +216,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 8, 16, 30},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
- [PORT_ALTR_16550_F64] = {
+ [UART_PORT_ALTR_16550_F64] = {
.name = "Altera 16550 FIFO64",
.fifo_size = 64,
.tx_loadsz = 64,
@@ -224,7 +224,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 16, 32, 62},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
- [PORT_ALTR_16550_F128] = {
+ [UART_PORT_ALTR_16550_F128] = {
.name = "Altera 16550 FIFO128",
.fifo_size = 128,
.tx_loadsz = 128,
@@ -237,7 +237,7 @@ static const struct serial8250_config uart_config[] = {
* workaround of errata A-008006 which states that tx_loadsz should
* be configured less than Maximum supported fifo bytes.
*/
- [PORT_16550A_FSL64] = {
+ [UART_PORT_16550A_FSL64] = {
.name = "16550A_FSL64",
.fifo_size = 64,
.tx_loadsz = 63,
@@ -245,7 +245,7 @@ static const struct serial8250_config uart_config[] = {
UART_FCR7_64BYTE,
.flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
},
- [PORT_RT2880] = {
+ [UART_PORT_RT2880] = {
.name = "Palmchip BK-3103",
.fifo_size = 16,
.tx_loadsz = 16,
@@ -253,7 +253,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
- [PORT_DA830] = {
+ [UART_PORT_DA830] = {
.name = "TI DA8xx/66AK2x",
.fifo_size = 16,
.tx_loadsz = 16,
@@ -262,7 +262,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
- [PORT_MTK_BTIF] = {
+ [UART_PORT_MTK_BTIF] = {
.name = "MediaTek BTIF",
.fifo_size = 16,
.tx_loadsz = 16,
@@ -270,7 +270,7 @@ static const struct serial8250_config uart_config[] = {
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
.flags = UART_CAP_FIFO,
},
- [PORT_NPCM] = {
+ [UART_PORT_NPCM] = {
.name = "Nuvoton 16550",
.fifo_size = 16,
.tx_loadsz = 16,
@@ -279,7 +279,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
- [PORT_SUNIX] = {
+ [UART_PORT_SUNIX] = {
.name = "Sunix",
.fifo_size = 128,
.tx_loadsz = 128,
@@ -287,7 +287,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 32, 64, 112},
.flags = UART_CAP_FIFO | UART_CAP_SLEEP,
},
- [PORT_ASPEED_VUART] = {
+ [UART_PORT_ASPEED_VUART] = {
.name = "ASPEED VUART",
.fifo_size = 16,
.tx_loadsz = 16,
@@ -295,7 +295,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
- [PORT_MCHP16550A] = {
+ [UART_PORT_MCHP16550A] = {
.name = "MCHP16550A",
.fifo_size = 256,
.tx_loadsz = 256,
@@ -303,7 +303,7 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {2, 66, 130, 194},
.flags = UART_CAP_FIFO,
},
- [PORT_BCM7271] = {
+ [UART_PORT_BCM7271] = {
.name = "Broadcom BCM7271 UART",
.fifo_size = 32,
.tx_loadsz = 32,
--
2.53.0