[PATCH] arm64: dts: renesas: ironhide: Describe inline ECC carveouts

[Marek Vasut]

The DBSC5 DRAM controller protects DRAM content using inline ECC.
The inline ECC utilizes areas of DRAM for its operation, which are
in the DRAM address range, but must not be accessed or modified.
Describe the inline ECC carveout areas used by the DBSC5 controller
on this hardware as reserved-memory, which must not be accessed.

In case of high DRAM utilization, unless the inline ECC carveouts
are properly reserved, Linux may use and corrupt the memory used
by the DBSC5 DRAM controller for inline ECC, which would lead to
the system becoming unstable.

Fixes: ad142a4ef710 ("arm64: dts: renesas: r8a78000: Add initial Ironhide board support")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
---
Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
Cc: Magnus Damm <magnus.damm@xxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: linux-kernel@xxxxxxxxxxxxxxx
Cc: linux-renesas-soc@xxxxxxxxxxxxxxx
---
 .../boot/dts/renesas/r8a78000-ironhide.dts    | 41 +++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
index d2b3fc08954a1..f073145a682bf 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -107,6 +107,47 @@ tee@8c400000 {
 			reg = <0x0 0x8c400000 0x0 0x02000000>;
 			no-map;
 		};
+
+		/* DRAM controller inline ECC areas */
+		ecc@10cccd0000 {
+			reg = <0x10 0xcccd0000 0x0 0x33330000>;
+			no-map;
+		};
+
+		ecc@12cccd0000 {
+			reg = <0x12 0xcccd0000 0x0 0x33330000>;
+			no-map;
+		};
+
+		ecc@14cccd0000 {
+			reg = <0x14 0xcccd0000 0x0 0x33330000>;
+			no-map;
+		};
+
+		ecc@16cccd0000 {
+			reg = <0x16 0xcccd0000 0x0 0x33330000>;
+			no-map;
+		};
+
+		ecc@18cccd0000 {
+			reg = <0x18 0xcccd0000 0x0 0x33330000>;
+			no-map;
+		};
+
+		ecc@1acccd0000 {
+			reg = <0x1a 0xcccd0000 0x0 0x33330000>;
+			no-map;
+		};
+
+		ecc@1ccccd0000 {
+			reg = <0x1c 0xcccd0000 0x0 0x33330000>;
+			no-map;
+		};
+
+		ecc@1ecccd0000 {
+			reg = <0x1e 0xcccd0000 0x0 0x33330000>;
+			no-map;
+		};
 	};
 };
 
-- 
2.53.0