[PATCH 3/4] arm64: dts: qcom: milos: add CPU interconnect properties
From: Luca Weiss
Date: Fri Jul 10 2026 - 05:31:43 EST
Add the interconnect entry for each CPU, with 2 different paths:
- CPU to DDR
- L3 Cache from CPU to DDR interface
Signed-off-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 41 +++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 1172a4f6adab..8e288b5dfc58 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -65,6 +66,11 @@ cpu0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_0: l2-cache {
@@ -98,6 +104,11 @@ cpu1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
};
@@ -118,6 +129,11 @@ cpu2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_2: l2-cache {
@@ -145,6 +161,11 @@ cpu3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
};
@@ -165,6 +186,11 @@ cpu4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_4: l2-cache {
@@ -192,6 +218,11 @@ cpu5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_5: l2-cache {
@@ -219,6 +250,11 @@ cpu6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_6: l2-cache {
@@ -246,6 +282,11 @@ cpu7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_7: l2-cache {
--
2.55.0