Re: [patch 17/48] x86/apic: Avoid the PVOPS indirection for the TSC deadline timer

[Artem Bityutskiy]

On Tue, 2026-02-24 at 17:36 +0100, Thomas Gleixner wrote:
> XEN PV does not emulate the TSC deadline timer, so the PVOPS indirection
> for writing the deadline MSR can be avoided completely.
> 
> Use native_wrmsrq() instead.
> 
> Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxx>
> ---
>  arch/x86/kernel/apic/apic.c |   13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -426,7 +426,7 @@ static int lapic_next_deadline(unsigned
>  	 */
>  	u64 tsc = rdtsc();
>  
> -	wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
> +	native_wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
>  	return 0;
>  }
>  
> @@ -450,7 +450,7 @@ static int lapic_timer_shutdown(struct c
>  	 * the timer _and_ zero the counter registers:
>  	 */
>  	if (v & APIC_LVT_TIMER_TSCDEADLINE)
> -		wrmsrq(MSR_IA32_TSC_DEADLINE, 0);
> +		native_wrmsrq(MSR_IA32_TSC_DEADLINE, 0);

Hi Thomas,

unfortunately for me and anyone who wants to trace
MSR_IA32_TSC_DEADLINE:

- wrmsrq() did trigger the 'write_msr' trace event.
- native_wrmsrq() does not trigger it.

I am not sure what is the best way to add the tracepoint back, but
before I even try, I wanted to ask if you would be OK with that.

Thank you!