Re: [PATCH v5 1/2] dt-bindings: remoteproc: document AMD MicroBlaze/V BRAM-based rproc

[Ben Levinsky]

Hi Mathieu 

Though 2/2 got NAK, will you still review this ? 

If not I will bump rev and update patch 2/2.

Thank you
Ben

On 7/9/26 7:57 AM, Ben Levinsky wrote:
> Describe an AMD MicroBlaze/V BRAM-based remote processor controlled
> through the remoteproc framework.
> 
> The binding models a soft-core processor subsystem instantiated in AMD
> programmable logic and using dual-port BRAM for firmware storage and
> execution. The remoteproc device is represented as a child node whose
> reg property describes the firmware memory window in the processor-local
> address space. The parent bus node provides standard devicetree address
> translation through ranges so Linux can access the same BRAM through the
> system physical address space.
> 
> A clock input feeds the soft-core processor subsystem, and an active-low
> reset GPIO holds the processor in reset until firmware loading completes.
> The firmware-name property is optional.
> 
> Reviewed-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> Signed-off-by: Ben Levinsky <ben.levinsky@xxxxxxx>
> ---
>  .../bindings/remoteproc/amd,bram-rproc.yaml   | 105 ++++++++++++++++++
>  1 file changed, 105 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml
> new file mode 100644
> index 000000000000..c0359f447ea8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/amd,bram-rproc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: AMD MicroBlaze/V BRAM-based Remote Processor
> +
> +maintainers:
> +  - Ben Levinsky <ben.levinsky@xxxxxxx>
> +
> +description: |
> +  Soft-core processor subsystem instantiated in AMD programmable logic and
> +  using dual-port BRAM for firmware storage and execution.
> +
> +  Hardware Architecture:
> +
> +    Host (PS)                        Programmable Logic (PL)
> +    =========                        ======================
> +
> +    AXI Interface -----------------> AXI BRAM Controller (Host Port)
> +                                             |
> +                                             | Port A
> +                                             v
> +                                     +-----------------+
> +                                     |  Dual-Port BRAM |
> +                                     | (shared memory) |
> +                                     +-----------------+
> +                                             ^
> +                                             | Port B
> +                                             |
> +                                     AXI BRAM Controller (Soft-core Port)
> +                                             ^
> +                                             | LMB
> +                                             |
> +                                     Soft-core CPU (MicroBlaze/V)
> +
> +    GPIO --------------------------> Proc Sys Reset ----> CPU Reset Signal
> +
> +    Clock -------------------------> Clock Distribution -> CPU Clock
> +
> +  Memory Architecture:
> +
> +    The dual-port BRAM allows simultaneous access from both processors:
> +      - Port A: Connected to the host AXI BRAM controller for firmware loading
> +      - Port B: Connected to the soft-core local memory bus for execution
> +
> +  The reg property describes the executable BRAM window in the processor-local
> +  address space. The parent bus node translates that window to the system
> +  physical address space by using standard devicetree address translation
> +  through ranges. A clock input and a reset GPIO control the subsystem.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: xlnx,zynqmp-bram-rproc
> +      - items:
> +          - enum:
> +              - amd,versal2-bram-rproc
> +              - xlnx,versal-bram-rproc
> +              - xlnx,versal-net-bram-rproc
> +          - const: xlnx,zynqmp-bram-rproc
> +
> +  reg:
> +    maxItems: 1
> +    description:
> +      Processor-local address and size of the BRAM firmware memory window,
> +      as seen by the soft-core processor (typically 0x0 for reset vector).
> +      The parent bus ranges property must translate this window to the
> +      corresponding system physical address.
> +
> +  clocks:
> +    maxItems: 1
> +    description:
> +      Clock input for the soft-core processor subsystem.
> +
> +  firmware-name:
> +    maxItems: 1
> +    description:
> +      Name of the firmware ELF file to load.
> +
> +  reset-gpios:
> +    maxItems: 1
> +    description:
> +      GPIO specifier controlling the soft-core reset input.
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - reset-gpios
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/gpio/gpio.h>
> +    remoteproc@0 {
> +      compatible = "xlnx,zynqmp-bram-rproc";
> +      reg = <0x0 0x40000>;
> +      clocks = <&pl_clk>;
> +      firmware-name = "firmware.elf";
> +      reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
> +    };
> +...