Re: [PATCH net-next 1/2] dt-bindings: net: add DAPU Telecom DAP8211R(I) PHY binding

[Rob Herring]

On Mon, Jul 13, 2026 at 04:12:22PM +0300, Artem Shimko wrote:
> Add device tree binding documentation for the DAPU Telecom DAP8211R(I)
> Gigabit Ethernet PHY.
> 
> The PHY supports TX and RX clock delays in 150 ps steps from 0 to 2250 ps,
> with a default of 1950 ps if not specified. The tx-inverted-clk flag
> provides a vendor-specific extension for boards where PCB trace length or
> MAC requirements necessitate 180-degree clock phase shift.
> 
> Signed-off-by: Artem Shimko <a.shimko.dev@xxxxxxxxx>
> ---
>  .../bindings/net/dapu,dap8211r.yaml           | 78 +++++++++++++++++++
>  1 file changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/dapu,dap8211r.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/dapu,dap8211r.yaml b/Documentation/devicetree/bindings/net/dapu,dap8211r.yaml
> new file mode 100644
> index 000000000000..208a82f779d6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/dapu,dap8211r.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/dapu,dap8211r.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY
> +
> +maintainers:
> +  - Artem Shimko <a.shimko.dev@xxxxxxxxx>
> +
> +description: |
> +  The DAP8211R(I) is a Gigabit Ethernet PHY with RGMII interface,
> +  supporting IEEE 802.3az Energy Efficient Ethernet, IEEE 1588 SyncE,
> +  and an internal packet generator for diagnostics.
> +
> +  Specifications:
> +    - 10BASE-Te, 100BASE-TX, 1000BASE-T
> +    - RGMII with configurable TX/RX clock delays (150 ps steps, 0-2250 ps)
> +    - IEEE 802.3az-2010 Energy Efficient Ethernet
> +    - IEEE 1588 SyncE support
> +    - Internal packet generator and checker for link diagnostics
> +
> +allOf:
> +  - $ref: ethernet-phy.yaml#
> +
> +properties:
> +  compatible:
> +    const: ethernet-phy-id0008.011b
> +
> +  reg:
> +    maxItems: 1
> +
> +  rx-internal-delay-ps:
> +    description:
> +      RGMII RX clock delay in picoseconds. The PHY supports 150 ps steps
> +      from 0 to 2250 ps. If not specified, defaults to 1950 ps. If the
> +      requested value does not exactly match a supported step, the driver
> +      selects the nearest supported value and issues a warning.
> +    enum: [0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500,
> +           1650, 1800, 1950, 2100, 2250]
> +    default: 1950
> +
> +  tx-internal-delay-ps:
> +    description:
> +      RGMII TX clock delay in picoseconds. The PHY supports 150 ps steps
> +      from 0 to 2250 ps. If not specified, defaults to 1950 ps. If the
> +      requested value does not exactly match a supported step, the driver
> +      selects the nearest supported value and issues a warning.
> +    enum: [0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500,
> +           1650, 1800, 1950, 2100, 2250]

This would also work:

multipleOf: 150
maximum: 2250

> +    default: 1950
> +
> +  tx-inverted-clk:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description:
> +      If present, the RGMII TX clock to the MAC is inverted (180 degree
> +      phase shift relative to the data lines). This is a vendor-specific
> +      extension for boards where PCB trace length or MAC requirements
> +      necessitate clock inversion. Only use this property after hardware
> +      signal integrity validation.
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    mdio {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        ethernet-phy@1 {
> +            compatible = "ethernet-phy-ieee802.3-c22";
> +            reg = <1>;
> +            rx-internal-delay-ps = <1050>;
> +            tx-internal-delay-ps = <1150>;
> +            tx-inverted-clk;
> +        };
> +    };
> \ No newline at end of file

With this fixed,

Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>