[RFC PATCH 01/22] dt-bindings: memory: cdns,k3-ddr: Add Cadence K3 DDR controller binding

[MANNURU VENKATESWARLU]

Add device tree binding for the Cadence DDR controller used in TI K3 SoCs.

Signed-off-by: Neha Malcom Francis <n-francis@xxxxxx>
Signed-off-by: Gandhar Deshpande <g-deshpande@xxxxxx>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@xxxxxx>
---
 .../memory-controllers/ti/cdns,k3-ddr.yaml    | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
new file mode 100644
index 0000000000000..89caeb111627a
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ti/cdns,k3-ddr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence DDR controller for K3 devices
+
+maintainers:
+  - Santhosh Kumar K <s-k6@xxxxxx>
+  - Neha Malcom Francis <n-francis@xxxxxx>
+
+properties:
+  compatible:
+    const: cdns,k3-ddr
+
+  reg:
+    minItems: 3
+    maxItems: 3
+    description: |
+      Address ranges for the different register regions of the DDRSS controller.
+      - ctl_cfg: Controller configuration registers
+      - ctl_cfg_pi: PHY Interface configuration registers
+      - ctl_cfg_phy: PHY configuration registers
+
+  reg-names:
+    items:
+      - const: ctl_cfg
+      - const: ctl_cfg_pi
+      - const: ctl_cfg_phy
+
+  bootph-pre-ram: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    cbass_main {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      memorycontroller: memorycontroller@2980000 {
+        compatible = "ti,j721e-ddrss";
+        reg = <0x0 0x02990000 0x0 0x4000>,
+              <0x0 0x0114000 0x0 0x100>;
+        reg-names = "cfg", "ctrl_mmr_lp4";
+        power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>,
+                        <&k3_pds 90 TI_SCI_PD_SHARED>;
+        interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+        ti,ddr-freq1 = <0>;
+        ti,ddr-freq2 = <0>;
+        ti,ddr-fhs-cnt = <0>;
+        clocks = <&k3_clks 47 2>, <&k3_clks 30 9>;
+        bootph-pre-ram;
+
+        ddr: ddr@0 {
+          compatible = "cdns,k3-ddr";
+          reg = <0x00 0x0000 0x00 0x72c>,
+                <0x00 0x2000 0x00 0x4b0>,
+                <0x00 0x4000 0x00 0x163c>;
+          reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+          bootph-pre-ram;
+        };
+
+        ddr_pmu0: ddr-pmu@100 {
+          compatible = "ti,k3-ddr-pmu";
+          reg = <0x00 0x100 0x00 0x14>;
+        };
+      };
+    };
-- 
2.34.1