Re: [PATCH RFC v2 0/9] Add System Controller support for RZ/T2H and RZ/N2H SoCs

[Lad, Prabhakar]

Hi Geert,

On Wed, Jul 15, 2026 at 9:54 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Tue, 14 Jul 2026 at 15:27, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > On Mon, Jul 13, 2026 at 5:00 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > > On Thu, 2 Jul 2026 at 14:31, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > > This series adds support for the System Controller (SYSC) blocks found on
> > > > the Renesas RZ/T2H and RZ/N2H SoCs. These blocks handle critical low-power
> > > > management and access control functions.
> > > >
> > > > Hardware Architecture & Dependency Challenges:
> > > > ----------------------------------------------
> > > > The SYSC in these SoCs is a multi-functional block responsible for:
> > > >     - Clock & Reset Control
> > > >     - Low Power Management
> > > >     - Clock Monitor (CLMA)
> > > >     - Access Control
> > > >
> > > > A key architectural detail is that these SYSC blocks are physically located
> > > > within the CPG/MSSR (Clock Pulse Generator / Module Standby Software Reset)
> > > > address space. While the CPG/MSSR driver is already implemented and
> > > > functional for these SoCs, the integration of SYSC adds a layer of
> > > > complexity due to a cyclic dependency:
> > > >     - SYSC requires CPG: The system controller needs a clock to operate.
> > > >     - CPG requires SYSC: Access control registers within the SYSC contain
> > > >       bits necessary to control the PLLs managed by the CPG.
> > > >
> > > > If implemented as a completely separate top-level system controller node, we
> > > > would face a cyclic dependency between the CPG and SYSC drivers during the
> > > > boot process.
> > > >
> > > > Proposed Implementation
> > > > ----------------------------
> > > > To resolve this, the SYSC blocks are represented as child nodes of the
> > > > CPG/MSSR controller in the device tree. The SYSC regmap is registered
> > > > directly against the CPG device node. This hierarchy correctly models the
> > > > hardware address space while allowing the drivers to share resources
> > > > without deadlock.
> > > >
> > > > I am sending this as an RFC specifically to get feedback on the
> > > > implementation of the SYSC as child nodes of the CPG to resolve the
> > > > dependency cycle.
> > >
> > > Personally, I am not a big fan of subnodes.  I assume you are using
> > > subnodes because you can register only a single regmap per syscon node?
> > Yes so that the consumers don't have to specify it by indexing.
> >
> > > Would it be possible to just extend the existing clock-controller
> > > node with two more reg entries, and expose them through a single
> > > combined regmap?
> > >
> > That should be possible. Or would you prefer just to extend the sizes
> > and create a single regmap for it?
> >
> >                cpg: clock-controller@80280000 {
> >                         compatible = "renesas,r9a09g077-cpg-mssr";
> > -                       reg = <0 0x80280000 0 0x10000>,
> > -                             <0 0x81280000 0 0x10000>;
> > +                       reg = <0 0x80280000 0 0x20000>,
> > +                             <0 0x81280000 0 0x20000>;
>
> Yes, as they are contiguous.
> These registers are not accessed unless there's a user specified in
> the DTB, right? So there is no issue when booting an old DTB that has
> the short reg blocks.
>
By checking the size of the resources, we decide whether to create a
regmap to maintain backward compatibility.

Cheers,
Prabhakar