[PATCH 0/2] clk: qcom: nord: fix PHY pipe clock halt check and mux ops

[Taniya Das]

Fix two PHY pipe clock issues in the Nord GCC/NE_GCC drivers: the
PCIe and USB3 pipe clock branches poll BRANCH_HALT_VOTED, which can
spuriously time out since the halt bit doesn't toggle reliably while
the PHY is down. The USB3 pipe clock source muxes use
clk_regmap_mux_closest_ops, which doesn't park on the reference clock
when disabled. Switch the branches to BRANCH_HALT_SKIP and convert
the muxes to clk_regmap_phy_mux_ops, matching existing conventions
elsewhere in the Qualcomm clock drivers.

Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
---
Taniya Das (2):
      clk: qcom: nord: use BRANCH_HALT_SKIP for PHY pipe clocks
      clk: qcom: negcc-nord: use clk_regmap_phy_mux for USB3 pipe clock srcs

 drivers/clk/qcom/gcc-nord.c   |  8 +++----
 drivers/clk/qcom/negcc-nord.c | 53 ++++++++++++-------------------------------
 2 files changed, 18 insertions(+), 43 deletions(-)
---
base-commit: b8809969e1d7a591e0f49dd464a5d04b3cf02ab1
change-id: 20260716-b4-nord-pipe-clk-fixes-e221e57f5600

Best regards,
-- 
Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>