Re: [PATCH v2] PCI: rzg3s-host: Re-enumerate the bus on PCIe link-state changes
From: Claudiu Beznea
Date: Thu Jul 16 2026 - 08:05:15 EST
Hi, Mani,
On 7/14/26 19:58, Manivannan Sadhasivam wrote:
On Tue, Jun 30, 2026 at 02:17:20PM +0000, John Madieu wrote:
The RZ/G3E PCIe controller does not expose the standard PCIe SlotThis is not correct. I don't see the patch configuring 'event IRQ' as a wakeup
Capability registers, so the generic pciehp driver cannot be used. The
only link-state signal the hardware provides is the DL_UpDown bit in the
PEIS0 event status register, which is raised on every Data Link layer
up/down transition.
Enable DL_UpDown in PEIE0 and hook up an interrupt handler so the driver
can react to link-state changes: a device that trains after boot gets
enumerated, and a device that disappears on link loss is removed. This
provides hotplug-like behaviour without the PCI hotplug core, which is
unavailable for the reason above.
On a DL_UpDown event the handler acks the W1C status bit and schedules a
worker that inspects PCSTAT1.DL_DOWN_STS:
- link up: re-run max link speed negotiation, wait for the link to
settle and pci_rescan_bus() the root bus;
- link down: walk the bus in reverse and
pci_stop_and_remove_bus_device() each child.
Both paths take pci_lock_rescan_remove() to serialise against the PCI
core.
Link events are only acted upon once the controller is fully
initialised. A DL_UpDown latched while the registers are not configured,
for example when the event IRQ is used as a system wakeup source during
resume, is acknowledged but does not schedule a rescan.
source.
Rest of the patch LGTM. If you confirm above, I can reword while applying.
John is not with Renesas anymore so I confirm on his behalf it is OK for you to amend it while applying.
However, I checked if this patch applies on top of next-20260715 or v7.2-rc1 and it doesn't on neither of these two HEADs.
I can re-base and re-send. Please let me know otherwise.
Thank you,
Claudiu