[PATCH v3 1/8] dt-bindings: clock: renesas: Split out RZ/T2H CPG binding

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Move the RZ/T2H and RZ/N2H clock controller bindings from the generic
renesas,cpg-mssr.yaml schema into a dedicated binding.

Unlike the traditional Renesas CPG/MSSR block, the RZ/T2H and RZ/N2H
system controller integrates additional functionality beyond clock and
module-stop control, including reset control, clock monitor support,
write-protection registers and other system management features.

Split the binding into a dedicated schema to describe these SoC-specific
features and requirements without complicating the generic CPG/MSSR
binding.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
v2->v3:
- new patch
---
 .../bindings/clock/renesas,cpg-mssr.yaml      | 27 +-----
 .../clock/renesas,rzt2h-cpg-mssr.yaml         | 87 +++++++++++++++++++
 2 files changed, 88 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg-mssr.yaml

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 655154534c0f..933316c34372 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -52,16 +52,9 @@ properties:
       - renesas,r8a779f0-cpg-mssr # R-Car S4-8
       - renesas,r8a779g0-cpg-mssr # R-Car V4H
       - renesas,r8a779h0-cpg-mssr # R-Car V4M
-      - renesas,r9a09g077-cpg-mssr # RZ/T2H
-      - renesas,r9a09g087-cpg-mssr # RZ/N2H
 
   reg:
-    minItems: 1
-    items:
-      - description: base address of register block 0
-      - description: base address of register block 1
-    description: base addresses of clock controller. Some controllers
-      (like r9a09g077) use two blocks instead of a single one.
+    maxItems: 1
 
   clocks:
     minItems: 1
@@ -108,24 +101,6 @@ required:
   - '#power-domain-cells'
 
 allOf:
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - renesas,r9a09g077-cpg-mssr
-              - renesas,r9a09g087-cpg-mssr
-    then:
-      properties:
-        reg:
-          minItems: 2
-        clock-names:
-          items:
-            - const: extal
-    else:
-      properties:
-        reg:
-          maxItems: 1
   - if:
       not:
         properties:
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg-mssr.yaml
new file mode 100644
index 000000000000..1b90289d61a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg-mssr.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,rzt2h-cpg-mssr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/T2H and RZ/N2H CPG/MSSR Block
+
+maintainers:
+  - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
+
+description: |
+  The Renesas RZ/T2H and RZ/N2H CPG/MSSR block is a multi-function block
+  where apart from clock and reset handling it supports other features.
+
+  These additional features include:
+    - Coordination with the Clock Monitor Array (CLMA) circuits to supervise frequency
+      integrity and initiate safe backup clock switching under fault conditions.
+    - Low-power state control registers (MSTPCR) that dictate module standby and core
+      sleep state transitions.
+    - Hardware write-protection logic (PRCRN/PRCRS registers).
+    - System-wide reset generation routing, debug counter halting, and module
+      configuration setups for PCIe and WDT IPs.
+
+properties:
+  compatible:
+    enum:
+      - renesas,r9a09g077-cpg-mssr # RZ/T2H
+      - renesas,r9a09g087-cpg-mssr # RZ/N2H
+
+  reg:
+    items:
+      - description: base address of register block in Non-Safety area
+      - description: base address of register block in Safety area
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: extal
+
+  '#clock-cells':
+    description: |
+      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+        and a core clock reference, as defined in
+        <dt-bindings/clock/*-cpg-mssr.h>
+      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+        a module number, as defined in the datasheet.
+    const: 2
+
+  '#power-domain-cells':
+    description:
+      SoC devices that are part of the CPG/MSSR Clock Domain and can be
+      power-managed through Module Standby should refer to the CPG device node
+      in their "power-domains" property, as documented by the generic PM Domain
+      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
+    const: 0
+
+  '#reset-cells':
+    description:
+      The single reset specifier cell must be the module number, as defined in
+      the datasheet.
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#power-domain-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@80280000 {
+        compatible = "renesas,r9a09g077-cpg-mssr";
+        reg = <0x80280000 0x20000>,
+              <0x81280000 0x20000>;
+        clocks = <&extal_clk>;
+        clock-names = "extal";
+        #clock-cells = <2>;
+        #power-domain-cells = <0>;
+        #reset-cells = <1>;
+    };
-- 
2.54.0