[PATCH v3 1/4] arm64: dts: qcom: Add support for usb nodes on Shikra
From: Krishna Kurapati
Date: Thu Jul 16 2026 - 12:35:40 EST
Add support for both USB controllers and their respective phys on Shikra.
Signed-off-by: Krishna Kurapati <krishna.kurapati@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 221 +++++++++++++++++++++++++++++++++++
1 file changed, 221 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 4e5bc9e17c8e..493c5d999d87 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
/ {
@@ -442,6 +443,85 @@ gcc: clock-controller@1400000 {
#power-domain-cells = <1>;
};
+ usb_1_hsphy: phy@1613000 {
+ compatible = "qcom,shikra-qusb2-phy";
+ reg = <0x0 0x01613000 0x0 0x180>;
+
+ clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ nvmem-cells = <&qusb2_hstx_trim_1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy: phy@1617000 {
+ compatible = "qcom,shikra-qusb2-phy";
+ reg = <0x0 0x01617000 0x0 0x180>;
+
+ clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+ nvmem-cells = <&qusb2_hstx_trim_2>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_qmpphy: phy@1615000 {
+ compatible = "qcom,shikra-qmp-usb3-dp-phy";
+ reg = <0x0 0x01615000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_EN>,
+ <&gcc GCC_AHB2PHY_USB_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ resets = <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
+ reset-names = "phy_phy",
+ "dp_phy",
+ "phy";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+ orientation-switch;
+
+ qcom,tcsr-reg = <&tcsr_regs 0xb244 0xb248>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+ };
+ };
+
system_noc: interconnect@1880000 {
compatible = "qcom,shikra-sys-noc";
reg = <0x0 0x01880000 0x0 0x6a080>;
@@ -493,6 +573,11 @@ qusb2_hstx_trim_1: hstx-trim@25b {
bits = <1 4>;
};
+ qusb2_hstx_trim_2: hstx-trim@25a {
+ reg = <0x25a 0x1>;
+ bits = <4 4>;
+ };
+
gpu_speed_bin: gpu-speed-bin@2006 {
reg = <0x2006 0x2>;
bits = <5 8>;
@@ -640,6 +725,142 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ usb_2: usb@4c00000 {
+ compatible = "qcom,shikra-dwc3", "qcom,snps-dwc3";
+ reg = <0x0 0x04c00000 0x0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <133333333>;
+
+ interrupts-extended = <&intc GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&mpm 59 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
+
+ iommus = <&apps_smmu 0x140 0x0>;
+
+ maximum-speed = "high-speed";
+
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+
+ power-domains = <&gcc GCC_USB20_GDSC>;
+
+ qcom,select-utmi-as-pipe-clk;
+ resets = <&gcc GCC_USB20_BCR>;
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+
+ usb-role-switch;
+ wakeup-source;
+
+ status = "disabled";
+
+ port {
+ usb_2_dwc3_hs: endpoint {
+ };
+ };
+ };
+
+ usb_1: usb@4e00000 {
+ compatible = "qcom,shikra-dwc3", "qcom,snps-dwc3";
+ reg = <0x0 0x04e00000 0x0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <133333333>;
+
+ interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&mpm 91 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 90 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ iommus = <&apps_smmu 0x120 0x0>;
+
+ phys = <&usb_1_hsphy>, <&usb_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy", "usb3-phy";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ snps,parkmode-disable-ss-quirk;
+
+ usb-role-switch;
+
+ wakeup-source;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
--
2.34.1