Re: [PATCH v9 10/11] Documentation/ABI: Document CXL Reset PCI reset method

[Alejandro Lucero Palau]

On 7/9/26 02:03, Srirangan Madhavan wrote:
> Document the "cxl_reset" PCI reset_method value for Type 2 CXL devices.
> CXL Reset is device scoped, requires affected memory to be idle,
> invalidates CPU caches, restores cached HDM decoder state, and does not
> request Memory Clear.
>
> Signed-off-by: Srirangan Madhavan <smadhavan@xxxxxxxxxx>
> ---
>   Documentation/ABI/testing/sysfs-bus-pci | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci
> index b767db2c52cb..5ab46a4340ae 100644
> --- a/Documentation/ABI/testing/sysfs-bus-pci
> +++ b/Documentation/ABI/testing/sysfs-bus-pci
> @@ -153,6 +153,20 @@ Description:
>   		"default" enables all supported reset methods in the
>   		default ordering.
>   
> +		If present, "cxl_reset" selects CXL Reset for CXL Type 2
> +		devices that advertise CXL Reset support and whose reset scope is
> +		limited to the selected PCI function.  The method is not listed
> +		when CXL Reset would affect another CXL.cache or CXL.mem function.


Not sure about CXL.cache, but as I replied to the cover letter, this 
last sentence is at least confusing. Only PF0 can enable/initialize 
CXL.mem so if there exists a memdev, any function using CXL will be 
affected ... but the reset can not happen because the range is in use by 
the PF0 initialization. If the reset can happen implies no PF is using it.


> +
> +		Before issuing CXL Reset, the kernel quiesces the PCI function,
> +		rejects the operation if cached HDM state is unavailable or
> +		affected CXL memory is busy, invalidates CPU caches for enabled
> +		HDM ranges, disables CXL.cache, and initiates cache write-back
> +		where supported.  After reset, the kernel restores PCI config
> +		state needed to access HDM MMIO, restores cached HDM decoder
> +		state, and completes PCI reset recovery.  "cxl_reset" does not
> +		request CXL Reset Memory Clear.
> +
>   What:		/sys/bus/pci/devices/.../reset
>   Date:		July 2009
>   Contact:	Michael S. Tsirkin <mst@xxxxxxxxxx>