Re: [PATCH v7 02/13] dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
From: Krzysztof Kozlowski
Date: Fri Jul 17 2026 - 02:37:00 EST
On Fri, Jul 17, 2026 at 12:35:38AM +0300, Stefan Dösinger wrote:
> diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml
> new file mode 100644
> index 000000000000..454997063573
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml
> @@ -0,0 +1,123 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/zte,zx297520v3-topcrm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ZTE zx297520v3 SoC top clock and reset controller
> +
> +maintainers:
> + - Stefan Dösinger <stefandoesinger@xxxxxxxxx>
> +
> +description: |
> + The zx297520v3 top clock and reset controller generates clocks for core
> + devices on the board like the main bus, USB and timers. In addition to clocks
> + it has reset controls for peripherals, a global board reset, watchdog reset
> + controls and a USB status register.
> +
> + The controller has two clock inputs: a 26 MHz and a 32 KHz external
> + oscillator. They need to be provided as input clocks. The controller provides
> + PLL output frequencies to downstream clock controllers.
> +
> + The USB PHY functionality is exposed as a child node documented in
> + zte,zx297520v3-usb-phy.yaml.
> +
> + All available clocks are defined as preprocessor macros in the
> + "include/dt-bindings/clock/zte,zx297520v3-clk.h" header. The resets are
> + defined in the "include/dt-bindings/reset/zte,zx297520v3-reset.h" header.
> +
> +properties:
> + compatible:
> + items:
> + - const: zte,zx297520v3-topcrm
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: 26 MHz external oscillator
> + - description: 32 KHz external oscillator
> +
> + clock-names:
> + items:
> + - const: osc26m
> + - const: osc32k
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + syscon-reboot:
> + type: object
> + $ref: /schemas/power/reset/syscon-reboot.yaml#
> + description:
> + Reboot method for the SoC.
> +
> + usb-phy@84:
No, do not children with and without addressing. syscon-reboot should
have address as well. Or this one should not, since it looks pretty
redundant - it is deducible from the top level compatible, no? So just
usb-phy.
> + compatible = "zte,zx297520v3-usb-phy";
> + type: object
> + $ref: /schemas/phy/zte,zx297520v3-usb-phy.yaml#
> + description:
> + USB and HSIC PHY controller.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - syscon-reboot
> + - usb-phy@84
> + - "#address-cells"
> + - "#size-cells"
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/reset/zte,zx297520v3-reset.h>
> + #include <dt-bindings/phy/phy-zte-zx297520v3-usb.h>
> + #include <dt-bindings/clock/zte,zx297520v3-clk.h>
> +
> + topcrm: clock-controller@13b000 {
> + compatible = "zte,zx297520v3-topcrm", "syscon";
> + reg = <0x0013b000 0x400>;
> + clocks = <&osc26m>, <&osc32k>;
> + clock-names = "osc26m", "osc32k";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> +
> + syscon-reboot {
> + compatible = "syscon-reboot";
> + offset = <0x0>;
> + mask = <0x1>;
> + value = <0x1>;
> + };
> +
> + usb-phy@84 {
> + reg = <0x84>;
> + interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
Here also misaligned.
> + interrupt-names = "usb-up", "usb-down", "hsic-up", "hsic-down";
> + resets = <&topcrm ZX297520V3_USB_PHY_RESET>,
> + <&topcrm ZX297520V3_HSIC_PHY_RESET>;
> + reset-names = "usb", "hsic";
> + #phy-cells = <1>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cb50c2e3b4ea..5f962b9947ab 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3878,10 +3878,13 @@ L: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx (moderated for non-subscribers)
> S: Odd fixes
> F: Documentation/arch/arm/zte/
> F: Documentation/devicetree/bindings/arm/zte.yaml
> +F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml
> F: Documentation/devicetree/bindings/phy/zte,zx297520v3-usb-phy.yaml
> F: arch/arm/boot/dts/zte/
> F: arch/arm/mach-zte/
> +F: include/dt-bindings/clock/zte,zx297520v3-clk.h
> F: include/dt-bindings/phy/phy-zte-zx297520v3-usb.h
> +F: include/dt-bindings/reset/zte,zx297520v3-reset.h
>
> ARM/ZYNQ ARCHITECTURE
> M: Michal Simek <michal.simek@xxxxxxx>
> diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
Same mistake. Filename MUST match the compatible.
> new file mode 100644
> index 000000000000..1f010ff4e6ca
> --- /dev/null
> +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
> @@ -0,0 +1,66 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) Stefan Dösinger.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_ZX297520V3_H
> +#define __DT_BINDINGS_CLOCK_ZX297520V3_H
> +
> +#define ZX297520V3_M0_WCLK 1
Start from 0 since you started resets also from 0.
> +#define ZX297520V3_SRAM1_PCLK 2
> +#define ZX297520V3_SRAM2_PCLK 3
> +#define ZX297520V3_UART0_WCLK 4
> +#define ZX297520V3_UART0_PCLK 5
> +#define ZX297520V3_I2C0_WCLK 6
> +#define ZX297520V3_I2C0_PCLK 7
> +#define ZX297520V3_RTC_WCLK 8
> +#define ZX297520V3_RTC_PCLK 9
> +#define ZX297520V3_LPM_GSM_WCLK 10
> +#define ZX297520V3_LPM_GSM_PCLK 11
> +#define ZX297520V3_LPM_LTE_WCLK 12
> +#define ZX297520V3_LPM_LTE_PCLK 13
> +#define ZX297520V3_LPM_TD_WCLK 14
> +#define ZX297520V3_LPM_TD_PCLK 15
> +#define ZX297520V3_LPM_W_WCLK 16
> +#define ZX297520V3_LPM_W_PCLK 17
> +#define ZX297520V3_TIMER_T08_WCLK 18
> +#define ZX297520V3_TIMER_T08_PCLK 19
> +#define ZX297520V3_TIMER_T09_WCLK 20
> +#define ZX297520V3_TIMER_T09_PCLK 21
> +#define ZX297520V3_MPLL 22
> +#define ZX297520V3_MPLL_D5 23
> +#define ZX297520V3_DPLL 24
> +#define ZX297520V3_GPLL 25
> +#define ZX297520V3_GPLL_D2 26
> +#define ZX297520V3_GATED_OSC26M 27
> +#define ZX297520V3_PMM_WCLK 28
> +#define ZX297520V3_PMM_PCLK 29
> +#define ZX297520V3_OUT0_WCLK 30
> +#define ZX297520V3_OUT1_WCLK 31
> +#define ZX297520V3_OUT2_WCLK 32
> +#define ZX297520V3_OUT32K_WCLK 33
> +#define ZX297520V3_RMIIPHY_WCLK 34
> +#define ZX297520V3_TIMER_T12_WCLK 35
> +#define ZX297520V3_TIMER_T12_PCLK 36
> +#define ZX297520V3_TIMER_T13_WCLK 37
> +#define ZX297520V3_TIMER_T13_PCLK 38
> +#define ZX297520V3_TIMER_T14_WCLK 39
> +#define ZX297520V3_TIMER_T14_PCLK 40
> +#define ZX297520V3_TIMER_T15_WCLK 41
> +#define ZX297520V3_TIMER_T15_PCLK 42
> +#define ZX297520V3_TIMER_T16_WCLK 43
> +#define ZX297520V3_TIMER_T16_PCLK 44
> +#define ZX297520V3_TIMER_T17_WCLK 45
> +#define ZX297520V3_TIMER_T17_PCLK 46
> +#define ZX297520V3_WDT_T18_WCLK 47
> +#define ZX297520V3_WDT_T18_PCLK 48
> +#define ZX297520V3_USIM1_WCLK 49
> +#define ZX297520V3_USIM1_PCLK 50
> +#define ZX297520V3_AHB_WCLK 51
> +#define ZX297520V3_AHB_PCLK 52
> +#define ZX297520V3_USB_WCLK 53
> +#define ZX297520V3_USB_PCLK 54
> +#define ZX297520V3_HSIC_WCLK 55
> +#define ZX297520V3_HSIC_PCLK 56
> +
> +#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
> diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h
> new file mode 100644
> index 000000000000..43db72bb59de
> --- /dev/null
> +++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h
Same here.
Best regards,
Krzysztof