[PATCH v2 2/2] arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths
From: Luca Weiss
Date: Fri Jul 17 2026 - 09:37:42 EST
Add the OSC L3 Cache controller node, interconnect entry for each CPU,
with 2 different paths (CPU to DDR, L3 Cache from CPU to DDR interface),
and add the OPP tables for each CPU clusters (cpu0-3, cpu4-6 & cpu7) to
permit scaling the DDR and L3 cache frequency by aggregating bandwidth
requests of all CPU core with reference to the current OPP they are
configured in by the LMH/EPSS hardware.
The effect is a proper caches & DDR frequency scaling when CPU cores
change frequency.
The OPP tables were built using the downstream memlat ddr & l3 tables
for each cluster type with the actual EPSS cpufreq LUT tables from
running devices. Note, that higher frequencies than SM7635 are available
on QCS6690, those have been added here as far as possible but may not be
fully complete. Additional OPPs may need to be added for that SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Signed-off-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 344 ++++++++++++++++++++++++++++++++++++
1 file changed, 344 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 8c9232988953..974afd7a582e 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -65,6 +66,13 @@ cpu0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_0: l2-cache {
@@ -98,6 +106,13 @@ cpu1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
};
@@ -118,6 +133,13 @@ cpu2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_2: l2-cache {
@@ -145,6 +167,13 @@ cpu3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
};
@@ -165,6 +194,13 @@ cpu4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_4: l2-cache {
@@ -192,6 +228,13 @@ cpu5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_5: l2-cache {
@@ -219,6 +262,13 @@ cpu6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_6: l2-cache {
@@ -246,6 +296,13 @@ cpu7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
+ operating-points-v2 = <&cpu7_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_7: l2-cache {
@@ -394,6 +451,281 @@ memory@0 {
reg = <0 0 0 0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-441600000 {
+ opp-hz = /bits/ 64 <441600000>;
+ opp-peak-kBps = <(547000 * 4) (364800 * 32)>;
+ };
+
+ opp-595200000 {
+ opp-hz = /bits/ 64 <595200000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(547000 * 4) (710400 * 32)>;
+ };
+
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <(547000 * 4) (806400 * 32)>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <(547000 * 4) (998400 * 32)>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <(547000 * 4) (998400 * 32)>;
+ };
+
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <(768000 * 4) (1094400 * 32)>;
+ };
+
+ opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <(768000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <(768000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1497600 * 32)>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1804800 * 32)>;
+ };
+ };
+
+ cpu4_opp_table: opp-table-cpu4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-peak-kBps = <(547000 * 4) (364800 * 32)>;
+ };
+
+ opp-633600000 {
+ opp-hz = /bits/ 64 <633600000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 768000 */
+ opp-peak-kBps = <(768000 * 4) (710400 * 32)>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 768000 */
+ opp-peak-kBps = <(768000 * 4) (710400 * 32)>;
+ };
+
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (902400 * 32)>;
+ };
+
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(1708000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1824000000 {
+ opp-hz = /bits/ 64 <1824000000>;
+ opp-peak-kBps = <(1708000 * 4) (1497600 * 32)>;
+ };
+
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2073600000 {
+ opp-hz = /bits/ 64 <2073600000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2707200000 {
+ opp-hz = /bits/ 64 <2707200000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1804800 * 32)>;
+ };
+ };
+
+ cpu7_opp_table: opp-table-cpu7 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-peak-kBps = <(547000 * 4) (364800 * 32)>;
+ };
+
+ opp-633600000 {
+ opp-hz = /bits/ 64 <633600000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(547000 * 4) (806400 * 32)>;
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-peak-kBps = <(547000 * 4) (806400 * 32)>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 768000 */
+ opp-peak-kBps = <(768000 * 4) (998400 * 32)>;
+ };
+
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 768000 */
+ opp-peak-kBps = <(768000 * 4) (998400 * 32)>;
+ };
+
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <(1555000 * 4) (998400 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(1555000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <(1708000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2304000000 {
+ opp-hz = /bits/ 64 <2304000000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2496000000 {
+ opp-hz = /bits/ 64 <2496000000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2707200000 {
+ opp-hz = /bits/ 64 <2707200000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1804800 * 32)>;
+ };
+
+ opp-2918400000 {
+ opp-hz = /bits/ 64 <2918400000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1804800 * 32)>;
+ };
+ };
+
pmu-a520 {
compatible = "arm,cortex-a520-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -2639,6 +2971,18 @@ rpmhpd_opp_turbo_l1: opp-416 {
};
};
+ epss_l3: interconnect@17d90000 {
+ compatible = "qcom,milos-epss-l3", "qcom,epss-l3";
+ reg = <0x0 0x17d90000 0x0 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPLL0>;
+ clock-names = "xo",
+ "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@17d91000 {
compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0x0 0x17d91000 0x0 0x1000>,
--
2.55.0