Re: [PATCH v2] EDAC/qcom: Skip ECC interrupt setup on Shikra, pre-configured by DSF

[Mukesh Ojha]

On Mon, Jul 13, 2026 at 03:28:52PM +0530, Faiyaz Mohammed wrote:
> On Shikra, the DDR System Firmware (DSF) configures ECC interrupt
> routing before the kernel driver probes — it enables Tag/Data RAM
> interrupts and programs error thresholds in the LLCC interrupt-enable
> registers.
> 
> Set irq_configured in shikra_cfg so that qcom_llcc_edac_probe() skips
> calling qcom_llcc_core_setup(), which would otherwise overwrite the
> firmware-managed register state with redundant writes.
> 
> Signed-off-by: Faiyaz Mohammed <faiyaz.mohammed@xxxxxxxxxxxxxxxx>
> ---
> Changes in v2:
> - Dropped [1/2] "soc: qcom: llcc: Add configuration data for Shikra SoC"
>   which was already merged via drivers-for-7.3.
> - Resend as standalone single-patch series.
> 
> Link: https://lore.kernel.org/all/20260630-shikra-edac-v1-0-287b3233241a@xxxxxxxxxxxxxxxx/
> ---
>  drivers/soc/qcom/llcc-qcom.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 22c8099cf6bb..733999867bbf 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -4595,6 +4595,7 @@ static const struct qcom_llcc_config shikra_cfg[] = {
>  		.size		= ARRAY_SIZE(shikra_data),
>  		.reg_offset	= llcc_v2_1_reg_offset,
>  		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +		.irq_configured = true,

Not related to the change but somehow it feels like the name could be more meaningful 
something like irq_fw_configured, anyways..

Reviewed-by: Mukesh Ojha <mukesh.ojha@xxxxxxxxxxxxxxxx>
-- 
-Mukesh Ojha