Re: [PATCH] ata: ahci_ceva: fix error paths in ceva_ahci_platform_enable_resources()

From: Damien Le Moal

Date: Fri Jul 17 2026 - 21:39:05 EST


On 7/18/26 03:25, Radhey Shyam Pandey wrote:
> On phy_init() failure the error path fell through to disable_rsts, which
> deasserted the controller reset and then entered disable_phys calling
> phy_power_off() on PHYs that were never powered on. That corrupts the PHY
> power_count and triggers an extra runtime PM put.
>
> Use a separate exit_phys path that unwinds with phy_exit() only and falls
> through to disable_clks while the controller remains in reset. Reserve
> phy_power_off() for the phy_power_on() failure path only, and skip
> masked-out ports in both unwind loops.
>
> On phy_power_on() failure re-assert the controller reset before disabling
> clocks and regulators, matching the teardown order used by
> ahci_platform_enable_resources() and ahci_platform_disable_resources().
>
> Fixes: 26c8404e162b ("ata: ahci_ceva: fix error handling for Xilinx GT PHY support")
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx>

Applied to for-7.2-fixes. Thanks!

--
Damien Le Moal
Western Digital Research