drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: incorrect type in argument 1 (different base types)
From: kernel test robot
Date: Sat Jul 18 2026 - 17:51:44 EST
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 94515f3a7d4256a5062176b7d6ed0471938cd51a
commit: 031cdd3bc3f369553933c1b0f4cb18000162c8ff kunit: Enable PCI on UML without triggering WARN()
date: 10 months ago
config: um-randconfig-r133-20260718 (https://download.01.org/0day-ci/archive/20260719/202607190503.J3EjpoyD-lkp@xxxxxxxxx/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
sparse: v0.6.5-rc1
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260719/202607190503.J3EjpoyD-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Fixes: 031cdd3bc3f3 ("kunit: Enable PCI on UML without triggering WARN()")
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202607190503.J3EjpoyD-lkp@xxxxxxxxx/
sparse warnings: (new ones prefixed by >>)
>> drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned long long [usertype] val @@ got restricted __be64 [addressable] [usertype] buf @@
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: expected unsigned long long [usertype] val
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: got restricted __be64 [addressable] [usertype] buf
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: cast from restricted __be64
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: cast from restricted __be64
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: cast from restricted __be64
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: cast from restricted __be64
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: cast from restricted __be64
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: cast from restricted __be64
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: cast from restricted __be64
drivers/i2c/busses/i2c-octeon-core.c:731:23: sparse: sparse: cast from restricted __be64
drivers/i2c/busses/i2c-octeon-core.c:732:42: sparse: sparse: cast from restricted __be64
vim +731 drivers/i2c/busses/i2c-octeon-core.c
63ef02da5ddb72 Aryan Srivastava 2025-03-25 688
63ef02da5ddb72 Aryan Srivastava 2025-03-25 689 /**
63ef02da5ddb72 Aryan Srivastava 2025-03-25 690 * octeon_i2c_hlc_block_comp_write - high-level-controller composite block write
63ef02da5ddb72 Aryan Srivastava 2025-03-25 691 * @i2c: The struct octeon_i2c
63ef02da5ddb72 Aryan Srivastava 2025-03-25 692 * @msgs: msg[0] contains address, msg[1] contains data to be written
63ef02da5ddb72 Aryan Srivastava 2025-03-25 693 *
63ef02da5ddb72 Aryan Srivastava 2025-03-25 694 * i2c core command is constructed and write data is written into the FIFO buffer.
63ef02da5ddb72 Aryan Srivastava 2025-03-25 695 * The execution of the command will result in HW write, using the data in FIFO.
63ef02da5ddb72 Aryan Srivastava 2025-03-25 696 * Used in the case where the i2c xfer is for greater than 8 bytes of write data.
63ef02da5ddb72 Aryan Srivastava 2025-03-25 697 *
63ef02da5ddb72 Aryan Srivastava 2025-03-25 698 * Returns: 0 on success, otherwise a negative errno.
63ef02da5ddb72 Aryan Srivastava 2025-03-25 699 */
63ef02da5ddb72 Aryan Srivastava 2025-03-25 700 static int octeon_i2c_hlc_block_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
63ef02da5ddb72 Aryan Srivastava 2025-03-25 701 {
63ef02da5ddb72 Aryan Srivastava 2025-03-25 702 bool set_ext;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 703 int ret;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 704 u16 len, i;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 705 u64 cmd, ext = 0;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 706
63ef02da5ddb72 Aryan Srivastava 2025-03-25 707 octeon_i2c_hlc_enable(i2c);
63ef02da5ddb72 Aryan Srivastava 2025-03-25 708 octeon_i2c_block_enable(i2c);
63ef02da5ddb72 Aryan Srivastava 2025-03-25 709
63ef02da5ddb72 Aryan Srivastava 2025-03-25 710 /* Write (size - 1) into block control register */
63ef02da5ddb72 Aryan Srivastava 2025-03-25 711 len = msgs[1].len - 1;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 712 octeon_i2c_writeq_flush((u64)len, i2c->twsi_base + OCTEON_REG_BLOCK_CTL(i2c));
63ef02da5ddb72 Aryan Srivastava 2025-03-25 713
63ef02da5ddb72 Aryan Srivastava 2025-03-25 714 /* Prepare core command */
63ef02da5ddb72 Aryan Srivastava 2025-03-25 715 cmd = SW_TWSI_V | SW_TWSI_SOVR | SW_TWSI_OP_7_IA;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 716 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 717
63ef02da5ddb72 Aryan Srivastava 2025-03-25 718 /* Set parameters for extended message (if required) */
63ef02da5ddb72 Aryan Srivastava 2025-03-25 719 set_ext = octeon_i2c_hlc_ext(i2c, msgs[0], &cmd, &ext);
63ef02da5ddb72 Aryan Srivastava 2025-03-25 720
63ef02da5ddb72 Aryan Srivastava 2025-03-25 721 /* Write msg into FIFO buffer */
63ef02da5ddb72 Aryan Srivastava 2025-03-25 722 octeon_i2c_writeq_flush(TWSX_BLOCK_STS_RESET_PTR,
63ef02da5ddb72 Aryan Srivastava 2025-03-25 723 i2c->twsi_base + OCTEON_REG_BLOCK_STS(i2c));
63ef02da5ddb72 Aryan Srivastava 2025-03-25 724 for (i = 0; i <= len; i += 8) {
63ef02da5ddb72 Aryan Srivastava 2025-03-25 725 __be64 buf = 0;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 726
63ef02da5ddb72 Aryan Srivastava 2025-03-25 727 /* Copy 8 bytes or remaining bytes from message buffer */
63ef02da5ddb72 Aryan Srivastava 2025-03-25 728 memcpy(&buf, &msgs[1].buf[i], min(8, msgs[1].len - i));
63ef02da5ddb72 Aryan Srivastava 2025-03-25 729
63ef02da5ddb72 Aryan Srivastava 2025-03-25 730 /* Byte-swap message data and write into FIFO */
63ef02da5ddb72 Aryan Srivastava 2025-03-25 @731 buf = cpu_to_be64(buf);
63ef02da5ddb72 Aryan Srivastava 2025-03-25 732 octeon_i2c_writeq_flush((u64)buf, i2c->twsi_base + OCTEON_REG_BLOCK_FIFO(i2c));
63ef02da5ddb72 Aryan Srivastava 2025-03-25 733 }
63ef02da5ddb72 Aryan Srivastava 2025-03-25 734 if (set_ext)
63ef02da5ddb72 Aryan Srivastava 2025-03-25 735 octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));
63ef02da5ddb72 Aryan Srivastava 2025-03-25 736
63ef02da5ddb72 Aryan Srivastava 2025-03-25 737 /* Send command to core (send data in FIFO) */
63ef02da5ddb72 Aryan Srivastava 2025-03-25 738 ret = octeon_i2c_hlc_cmd_send(i2c, cmd);
63ef02da5ddb72 Aryan Srivastava 2025-03-25 739 if (ret)
63ef02da5ddb72 Aryan Srivastava 2025-03-25 740 goto err;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 741
63ef02da5ddb72 Aryan Srivastava 2025-03-25 742 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
63ef02da5ddb72 Aryan Srivastava 2025-03-25 743 if ((cmd & SW_TWSI_R) == 0) {
63ef02da5ddb72 Aryan Srivastava 2025-03-25 744 octeon_i2c_block_disable(i2c);
63ef02da5ddb72 Aryan Srivastava 2025-03-25 745 return octeon_i2c_check_status(i2c, false);
63ef02da5ddb72 Aryan Srivastava 2025-03-25 746 }
63ef02da5ddb72 Aryan Srivastava 2025-03-25 747
63ef02da5ddb72 Aryan Srivastava 2025-03-25 748 err:
63ef02da5ddb72 Aryan Srivastava 2025-03-25 749 octeon_i2c_block_disable(i2c);
63ef02da5ddb72 Aryan Srivastava 2025-03-25 750 return ret;
63ef02da5ddb72 Aryan Srivastava 2025-03-25 751 }
63ef02da5ddb72 Aryan Srivastava 2025-03-25 752
:::::: The code at line 731 was first introduced by commit
:::::: 63ef02da5ddb725555cd41f125ec0bd8e893da3a i2c: octeon: add block-mode i2c operations
:::::: TO: Aryan Srivastava <aryan.srivastava@xxxxxxxxxxxxxxxxxxx>
:::::: CC: Andi Shyti <andi@xxxxxxxx>
--
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