[tip: x86/msr] x86/mce: Work around build warning after MSR-interface switch

[tip-bot2 for Juergen Gross]

The following commit has been merged into the x86/msr branch of tip:

Commit-ID:     a7187ca1e72505fd6785b0ce537ae066773a5532
Gitweb:        https://git.kernel.org/tip/a7187ca1e72505fd6785b0ce537ae066773a5532
Author:        Juergen Gross <jgross@xxxxxxxx>
AuthorDate:    Fri, 03 Jul 2026 12:55:55 +02:00
Committer:     Ingo Molnar <mingo@xxxxxxxxxx>
CommitterDate: Sun, 19 Jul 2026 11:39:18 +02:00

x86/mce: Work around build warning after MSR-interface switch

The recent switch to 64-bit MSR interfaces introduced a build warning.

Work it around with a __maybe_unused annotation. After the full conversion
of the APIs we'll be able to address this more robustly by making sure
the APIs consume all the values as far the compiler is concerned, so that
the compiler doesn't emit such nuisance warnings.

[ mingo: Updated the changelog. ]

Fixes: cff219368bd0 ("x86/mce: Stop using 32-bit MSR interfaces")
Closes: https://lore.kernel.org/oe-kbuild-all/202607031726.ZOwu4snu-lkp@xxxxxxxxx/
Reported-by: kernel test robot <lkp@xxxxxxxxx>
Signed-off-by: Juergen Gross <jgross@xxxxxxxx>
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
Link: https://patch.msgid.link/20260703105555.1758819-1-jgross@xxxxxxxx
---
 arch/x86/kernel/cpu/mce/p5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c
index eb99f38..3c2b6cc 100644
--- a/arch/x86/kernel/cpu/mce/p5.c
+++ b/arch/x86/kernel/cpu/mce/p5.c
@@ -44,7 +44,7 @@ noinstr void pentium_machine_check(struct pt_regs *regs)
 /* Set up machine check reporting for processors with Intel style MCE: */
 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
 {
-	u64 q;
+	u64 __maybe_unused q;
 
 	/* Default P5 to off as its often misconnected: */
 	if (!mce_p5_enabled)