Re: [PATCH v6 2/3] hwmon: (applesmc) Fix lockless cache validation data race

[Guenter Roeck]

On Sat, Jul 11, 2026 at 05:33:22PM +0800, Shih-Yuan Lee wrote:
> In applesmc_get_entry_by_index(), the cache->valid flag is checked
> locklessly, but setting it to true lacks memory barriers. This can lead to
> a data race (TOCTOU) where another thread sees cache->valid as true
> before the actual cache contents (cache->key, cache->len, cache->type, etc.)
> are fully committed and visible to that CPU, potentially causing it to read
> uninitialized data and send incorrect keys to the Apple SMC hardware.
> 
> Introduce memory barriers (smp_load_acquire and smp_store_release) with
> explanatory comments to ensure cache synchronization is thread-safe and
> fully visible across all CPUs.
> 
> Signed-off-by: Shih-Yuan Lee <fourdollars@xxxxxxxxxx>

Applied.

Thanks,
Guenter