Re: [PATCH v5 0/3] spi: tegra210-quad: Improve interrupt handling for loaded systems

[Mark Brown]

On Wed, Jul 08, 2026 at 01:12:54AM +0000, Vishwaroop A wrote:
> The current threaded IRQ implementation in spi-tegra210-quad suffers from
> scheduler-induced latency on heavily loaded systems. Because threaded IRQ
> handlers are subject to CFS scheduling, they can be delayed long enough to
> trigger transfer timeouts even though hardware completes in microseconds.
> This results in false timeout errors and WARN_ON splats during normal
> operation.

Is the handling for timeouts with DMA transfers that get split or
chained together safe?  handle_dma_based_xfer() starts a new DMA after
the current one completes if there's more work to do but it looks like
_combined_seq_xfer() will clear curr_xfer if we didn't get an error from
handling the timeout.

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