Re: [PATCH v5 3/3] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY

From: Qiang Yu

Date: Sun Jul 19 2026 - 23:44:27 EST


On Fri, Jul 17, 2026 at 06:50:23PM +0200, Konrad Dybcio wrote:
> On 7/17/26 11:58 AM, Qiang Yu wrote:
> > Glymur's PCIe3a and PCIe3b controllers share a single Gen5x8 QMP PHY block
> > that can be bifurcated into two independent x4 links, rather than each
> > controller owning its own dedicated PHY.
> >
> > Add a pcie3_phy node describing the shared PHY block, add the missing
> > PCIe3a controller node, and point both PCIe3a's and PCIe3b's port phys
> > at &pcie3_phy (index 0 and 1 respectively) so each controller picks up
> > its half of the bifurcated PHY. Update the GCC pipe clock parent array
> > to reference the new PHY's clock outputs instead of the placeholders.
> >
> > Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 8 +
> > arch/arm64/boot/dts/qcom/glymur.dtsi | 336 ++++++++++++++++++++++++++++++-
>
> These changes really shouldn't be in the same commit

Ack, will split this into two patches: one for the glymur.dtsi PHY node
and GCC pipe clock changes, and a separate one for the glymur-crd.dtsi
board-specific supply wiring.

>
> > 2 files changed, 342 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> > index c12808abbfe1..e8e81bf9a6a1 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> > @@ -750,6 +750,14 @@ &pcie3b {
> > pinctrl-names = "default";
> > };
> >
> > +&pcie3_phy {
> > + vdda-phy-supply = <&vreg_l3c_e1_0p89>;
> > + vdda-pll-supply = <&vreg_l2c_e1_1p14>;
> > +
> > + vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>;
> > + vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>;
> > +};
>
> This node is disabled

Yes, it is disabled because pcie3b is not enabled by default.
See the fake pcie3b_phy be dropped

https://lore.kernel.org/all/20260420133616.88740-2-krzysztof.kozlowski@xxxxxxxxxxxxxxxx/

- Qiang Yu