Re: [PATCH RFC 2/2] irqchip/ls-scfg-msi: enable multi-MSI allocation

[Thomas Gleixner]

On Thu, Jul 16 2026 at 12:15, Alexander Wilhelm wrote:
> Add MSI_FLAG_MULTI_PCI_MSI to the parent domain's supported flags so PCI
> devices can request more than one contiguous MSI vector. The previous
> refactor to bitmap_find_free_region() already handles arbitrary
> power-of-two orders, so drop the WARN_ON(nr_irqs != 1) guard.

Same comment vs. changelog as before.

> In practice, multi-MSI requires the 'no-affinity' MSIR routing, because
> affinity mode only releases every (1 << ibs_shift)-th hwirq and therefore
> cannot satisfy aligned power-of-two blocks larger than one bit. Statically
> pin each MSIR's chained parent IRQ to its matching CPU in that mode: the
> low ibs_shift bits of the hwirq then select both the MSIR and the target
> CPU, giving each MSI vector a deterministic target CPU without runtime
> migration.

> +	} else {
>  		msir->srs = index;
> +		/* Statically pin each MSIR to its matching CPU */

This wants some explanation of the WHY in the comment.

> +		if (index < num_possible_cpus())
> +			irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
> +	}

Thanks,

        tglx