Re: [PATCH 3/3] nvmem: mtk-efuse: add mt6572 support

[Roman Vivchar]

Hi Angelo,

On Monday, July 20th, 2026 at 3:48 PM, AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> wrote:

> On 7/15/26 16:27, Roman Vivchar via B4 Relay wrote:
> > From: Roman Vivchar <rva333@xxxxxxxxxxxxxx>
> >
> > Add a platform data struct for the efuse controller.
> >
> > Signed-off-by: Roman Vivchar <rva333@xxxxxxxxxxxxxx>
> > ---
> >   drivers/nvmem/mtk-efuse.c | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
> > index 1462f2760818..a79434608465 100644
> > --- a/drivers/nvmem/mtk-efuse.c
> > +++ b/drivers/nvmem/mtk-efuse.c
> > @@ -124,6 +124,11 @@ static int mtk_efuse_probe(struct platform_device *pdev)
> >   	return 0;
> >   }
> >
> > +static const struct mtk_efuse_pdata mtk_mt6572_efuse_pdata = {
> > +	.uses_post_processing = false,
>
> Are you sure this SoC (or any other compatible with it) doesn't have any GPU speed
> binning?
>
> If you're really sure
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>

It does, but we can't really rely on it. The GPU is complicated here...

Something like this:
- mfgcfg
  ^- mfg_pre ('safe' UNIVPLL div or 'unsafe' mfg mux)
     ^- mfg (if you're here and your chip is NOT mt6572w then be prepared
	         for crashes)
        ^- whpll (or any other parent, but downstream uses WHPLL as GPU
                  clock source)

There is GPU speedbin, but it means either GPU scaling is fine and mfg
mux is safe (0, unfused) or that the GPU must stay at UNIVPLL divider
(1, fused off).

My current solution is using assigned-clocks and assigned-clock-parents
in the each board which we've tested manually.
&gpu {
        /* Switch to WHPLL */
        assigned-clocks = <&topckgen CLK_TOP_MFG_SEL>,
                          <&topckgen CLK_TOP_MFG_PRE_SEL>;
        assigned-clock-parents = <&topckgen CLK_TOP_MFG_PRE_500M>,
                                 <&topckgen CLK_TOP_MFG_SEL>;

        operating-points-v2 = <&gpu_opp_table>;
        nvmem-cells = <&gpu_speedbin>;
        nvmem-cell-names = "speedbin";
		status = "okay";
};

On boards with GPU frequency fused off the entire setup is omitted
except status = "okay";

Let me know if you have some other idea how this should be handled.

Best regards,
Roman