Re: [PATCH v5 5/5] arm64: dts: allwinner: sun55i: add thermal sensors

[Chen-Yu Tsai]

On Sun, Jul 5, 2026 at 1:16 AM Mikhail Kalashnikov <iuncuim@xxxxxxxxx> wrote:
>
> The A523 processor has two temperature controllers, THS0 and THS1.
> THS0 has only one temperature sensor, which is located in the DRAM
> controller.
>
> THS1 does have 3 sensors:
> ths1_0 - "big" cores
> ths1_1 - "little" cores
> ths1_2 - gpu
>
> Add the thermal sensor configuration and the thermal zones.
> Trips temperature, polling-delay and sustainable-power parameters are
> derived from the manufacturer's BSP.
>
> Signed-off-by: Mikhail Kalashnikov <iuncuim@xxxxxxxxx>
> ---
>  .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 160 ++++++++++++++++++
>  1 file changed, 160 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> index ca6a16807..2ed00e7a7 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi

[...]

> @@ -355,6 +364,32 @@ gpadc: adc@2009000 {
>                         status = "disabled";
>                 };
>
> +               ths1: thermal-sensor@2009400 {
> +                       compatible = "allwinner,sun55i-a523-ths1";
> +                       reg = <0x02009400 0x400>;
> +                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>;
> +                       clock-names = "bus", "mod";
> +                       resets = <&ccu RST_BUS_THS>;
> +                       nvmem-cells = <&ths_calibration0>, <&ths_calibration1>;
> +                       nvmem-cell-names = "calibration",
> +                                    "calibration-second-part";

Just put them on one line. We can go up to 100 characters wide.

> +                       #thermal-sensor-cells = <1>;
> +               };
> +
> +               ths0: thermal-sensor@200a000 {
> +                       compatible = "allwinner,sun55i-a523-ths0";
> +                       reg = <0x0200a000 0x400>;
> +                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>;
> +                       clock-names = "bus", "mod";
> +                       resets = <&ccu RST_BUS_THS>;
> +                       nvmem-cells = <&ths_calibration0>, <&ths_calibration1>;
> +                       nvmem-cell-names = "calibration",
> +                                    "calibration-second-part";

Same here.

> +                       #thermal-sensor-cells = <0>;
> +               };
> +
>                 wdt: watchdog@2050000 {
>                         compatible = "allwinner,sun55i-a523-wdt";
>                         reg = <0x2050000 0x20>;
> @@ -586,6 +621,14 @@ sid: efuse@3006000 {
>                         reg = <0x03006000 0x1000>;
>                         #address-cells = <1>;
>                         #size-cells = <1>;
> +
> +                       ths_calibration0: ths-calibration0@38 {
> +                               reg = <0x38 0x8>;
> +                       };
> +
> +                       ths_calibration1: ths-calibration1@44 {
> +                               reg = <0x44 0x8>;
> +                       };
>                 };
>
>                 gic: interrupt-controller@3400000 {
> @@ -1102,4 +1145,121 @@ npu: npu@7122000 {
>                         power-domains = <&ppu PD_NPU>;
>                 };
>         };
> +
> +       thermal-zones {
> +               cpu0_thermal: cpu0-thermal {

There is no reference to this or the other labels for the thermal zones.
Please drop them.

[...]

> +               gpu-thermal {
> +                       polling-delay-passive = <100>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&ths1 2>;
> +                       sustainable-power = <2400>;
> +
> +                       gpu-trips {

As mentioned by Sashiko, the trips container node must be named "trips".
This is also required by the thermal zone binding.

[...]


Thanks
ChenYu