Re: [PATCH v1 1/1] nvme-pci: adaptive interrupt coalescing

[Keith Busch]

On Tue, Jul 21, 2026 at 04:37:39PM +0800, Fengnan Chang wrote:
> @@ -1618,6 +1748,8 @@ static inline bool nvme_poll_cq(struct nvme_queue *nvmeq,
>  		 * the cqe requires a full read memory barrier
>  		 */
>  		dma_rmb();
> +		if (sq_head)
> +			*sq_head = le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].sq_head);

This is the wrong criteria to determine the outstanding depth. The spec
allows the controller to move this forward after it has read an entry.
The commands may still be in progress, so the depth of future
completions to expect can't depend on this value.

But in general, I agree with the spirit of where this is going.

For MSI, you can make use of the INTMS/INTMC NVMe registers to make this
even more efficient. Your patch disables the irq at the cpU level, but
the device is still emitting those messages for no reason.