Re: [PATCH v4 2/3] clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc

[Alexandre Mergnat]

On Tue, 21 Jul 2026 10:13:55 +0800, Joey Lu <a0987203069@xxxxxxxxx> wrote:
> PLL_CTL1_FRAC was defined as GENMASK(31, 24), covering only 8 bits.
> The hardware fractional field occupies bits [31:8] (24 bits), so the
> mask must be GENMASK(31, 8).
> 
> The previous fractional-mode calculation used FIELD_MAX(PLL_CTL1_FRAC)
> as the denominator to obtain 2 decimal places.  With the corrected 24-bit
> mask the old divisor is wrong; replace the arithmetic with a proper
> 24-bit fixed-point rounding to 3 decimal places using the kernel's
> DIV_ROUND_CLOSEST_ULL helper:
> 
> [...]

Reviewed-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>

-- 
Alexandre Mergnat <amergnat@xxxxxxxxxxxx>