Re: [PATCH] drm/msm/dpu: Fix DMA SSPP REC block offsets on DPU v13

[Dmitry Baryshkov]

On Mon, Jul 20, 2026 at 03:56:08PM +0800, Yongxing Mou wrote:
> On DPU v13, the DMA SSPP REC0 and REC1 blocks are located at
> offsets 0x1000 and 0x3000 from the SSPP common base.
> 
> The existing DMA SSPP sub-block descriptor does not initialize
> sspp_rec0_blk and sspp_rec1_blk, causing REC register accesses
> to be performed at offset 0 instead of the corresponding REC
> block. As a result, DMA SSPP pipes are not programmed correctly
> and fail to produce output.
> 
> Introduce a DPU v13 specific DMA SSPP descriptor with the correct
> REC block offsets and use it for all DMA SSPPs in the Kaanapali
> catalog.
> 
> Signed-off-by: Yongxing Mou <yongxing.mou@xxxxxxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h | 12 ++++++------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c             | 12 ++++++++++++
>  2 files changed, 18 insertions(+), 6 deletions(-)

Fixes: 83fe2cd56b1d ("drm/msm/dpu: Add support for Kaanapali DPU")

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>



-- 
With best wishes
Dmitry