Re: [PATCH v13 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema

[Vladimir Zapolskiy]

Hi Frank.

On 7/21/26 21:57, Frank Li wrote:
> On Mon, Jul 20, 2026 at 02:11:34AM +0100, Bryan O'Donoghue wrote:
> > Add a base schema for the MIPI CSI2 PHYs on Qualcomm SoCs. This PHY
> > supports both DPHY and CPHY operation. A special mode of DPHY operation -
> > called variously split-mode or combo-mode also allows for two sensors to be
> > connected to one PHY.
> >
> > The submitted binding here describes the DPHY modes of operation only. CPHY
> > is left to future work.
> >
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
> > ---
> >   .../bindings/phy/qcom,x1e80100-csi2-phy.yaml       | 195 +++++++++++++++++++++
> >   1 file changed, 195 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> > new file mode 100644
> > index 0000000000000..880fe602945cb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> > @@ -0,0 +1,195 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm X1E80100 SoC CSI2 PHY
> > +
> > +maintainers:
> > +  - Bryan O'Donoghue <bod@xxxxxxxxxx>
> > +
> > +description:
> > +  Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors
> > +  to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY
> > +  modes.
> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,x1e80100-csi2-phy
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  "#phy-cells":
> > +    const: 1
> > +    description:
> > +      The single cell specifies the PHY operating mode.
> > +
> > +  clocks:
> > +    maxItems: 3
> > +
> > +  clock-names:
> > +    items:
> > +      - const: core
> > +      - const: timer
> > +      - const: ahb
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  operating-points-v2: true
> > +
> > +  opp-table:
> > +    type: object
> > +
> > +  power-domains:
> > +    items:
> > +      - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
> > +      - description: MMCX voltage rail
> > +      - description: MXC or MXA voltage rail
> > +
> > +  power-domain-names:
> > +    items:
> > +      - const: top
> > +      - const: mmcx
> > +      - const: mx
> > +
> > +  vdda-0p9-supply:
> > +    description: Phandle to a 0.9V regulator supply to a PHY.
> > +
> > +  vdda-1p2-supply:
> > +    description: Phandle to 1.2V regulator supply to a PHY.
> > +
> > +  ports:
> > +    $ref: /schemas/graph.yaml#/properties/ports
> > +
> > +    properties:
> > +      port@0:
> > +        $ref: /schemas/graph.yaml#/$defs/port-base
> > +        description:
> > +          Sensor input. Always present. A single sensor is described by a
> > +          single endpoint with one to four data lanes. DPHY split mode,
> > +          where two independent sensors share the same PHY, is described
> > +          by two endpoints; endpoint@0 with exactly two data-lanes and
> > +          endpoint@1 with exactly one data-lane.
>
> Sorry, jump in so late. I have questions about this design
>
> why not model each lane as sperated phys.
>
> csi1 {
> 	...
> 	phys = <&phy 0>, <&phy 1>; // use lane 0 and 1, connect sensor 1
> };
>
> csi2 {
> 	...
> 	phys = <&phy 2>; // use lan 2, connect sensor 2.
> };

Such design has a number of flaws and in general it looks overly
complicated. From the beginning it's unclear how to distinguish
a clock lane from a data lane, how to specify lane frequencies etc.

--
Best wishes,
Vladimir