[PATCH RFC v2 2/2] irqchip/ls-scfg-msi: enable multi-MSI allocation

[Alexander Wilhelm]

PCI endpoints that ask for a contiguous multi-vector MSI block currently
fall back to single-MSI on Layerscape SCFG and multiplex every device
interrupt onto one CPU. The hwirq allocator already reserves
order-aligned power-of-two regions, but the parent domain does not
advertise multi-MSI support and a leftover single-vector guard rejects
any request for more than one vector.

Simply lifting those two restrictions is not enough. A multi-vector
block spans several MSIRs by construction of the hwirq layout, and in
no-affinity routing mode every MSIR's chained parent IRQ defaults to
CPU0 with no way to rebalance individual MSIs at runtime. Allowing
nr_irqs > 1 without a distribution hint would therefore pile all
vectors of a single device onto the boot CPU and defeat the per-CPU
scaling that multi-MSI is supposed to buy.

Advertise multi-MSI support on the parent domain and let the allocator
serve requests larger than one vector. Distribute the MSIR chained
parent IRQs across the online CPUs via a modular round-robin at setup,
so that multi-MSI-capable devices see genuine per-CPU parallelism
instead of piling every interrupt onto CPU0.

Assisted-by: Copilot:claude-opus-4.7
Signed-off-by: Alexander Wilhelm <alexander.wilhelm@xxxxxxxxxxxx>
---
 drivers/irqchip/irq-ls-scfg-msi.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index 50bd84644769..6c05af6b3fa2 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -60,6 +60,7 @@ struct ls_scfg_msi {
 #define MPIC_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
 				 MSI_FLAG_USE_DEF_CHIP_OPS)
 #define MPIC_MSI_FLAGS_SUPPORTED (MSI_FLAG_PCI_MSIX       | \
+				  MSI_FLAG_MULTI_PCI_MSI  | \
 				  MSI_GENERIC_FLAGS_MASK)
 
 static const struct msi_parent_ops ls_scfg_msi_parent_ops = {
@@ -145,8 +146,6 @@ static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
 	unsigned int i;
 	int pos, err;
 
-	WARN_ON(nr_irqs != 1);
-
 	scoped_guard(spinlock, &msi_data->lock)
 		pos = bitmap_find_free_region(msi_data->used, msi_data->irqs_num, order);
 
@@ -267,8 +266,16 @@ static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
 		/* Associate MSIR interrupt to the cpu */
 		irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
 		msir->srs = 0; /* This value is determined by the CPU */
-	} else
+	} else {
 		msir->srs = index;
+		/*
+		 * Distribute MSI processing across all CPUs so heavy traffic is
+		 * not throttled by a single core saturating on interrupts.
+		 * No-affinity mode disables per-IRQ rebalancing and without a
+		 * hint here every MSIR's chained handler would default to CPU0.
+		 */
+		irq_set_affinity(msir->gic_irq, get_cpu_mask(index % num_possible_cpus()));
+	}
 
 	/* Release the hwirqs corresponding to this MSIR */
 	if (!msi_affinity_flag || msir->index == 0) {

-- 
2.43.0