Re: [PATCH net v2] mlxsw: pci: Quiesce EQ tasklet and CQ NAPI before teardown

[Petr Machata]

Myeonghun Pak <mhun512@xxxxxxxxx> writes:

> mlxsw_pci_eq_irq_handler() schedules the EQ tasklet. The tasklet reads
> the EQ ring and schedules CQ NAPI instances. The CQ poll callbacks, in
> turn, dereference the RDQ or SDQ associated with the CQ.
>
> mlxsw_pci_fini() unregisters the IRQ and immediately tears down the
> asynchronous queues in RDQ, SDQ, CQ, EQ order. free_irq() waits for IRQ
> handlers, but not for a tasklet already scheduled by one. In addition,
> mlxsw_pci_cq_fini() disables each CQ NAPI only after all RDQs and SDQs
> have been freed. A pending tasklet or NAPI poll can therefore access
> freed queue storage.
>
> Kill the EQ tasklet after free_irq() so it cannot schedule any more CQ
> NAPI instances. Disable all CQ NAPI instances before freeing the first
> descriptor queue, ensuring their poll callbacks have completed. Track
> the enabled state per CQ to avoid disabling a NAPI instance twice when
> the CQ is later destroyed, while preserving the partial initialization
> unwind.
>
> Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation")

Please leave at least 24 hours between submissions. I'll look at the
patch in more detail, but wanted to get this out before you send a v3.

Seeing you cite the commit that actually added this code, this never
worked, is therefore no regression, and should be aimed at next instead
of net / stable.

> Cc: stable@xxxxxxxxxxxxxxx
> Co-developed-by: Ijae Kim <ae878000@xxxxxxxxx>
> Signed-off-by: Ijae Kim <ae878000@xxxxxxxxx>
> Signed-off-by: Myeonghun Pak <mhun512@xxxxxxxxx>
> ---
> v2:
> - Fix typo in napi_enabled assignment reported by kernel test robot.
>
> v1: https://lore.kernel.org/r/20260721062105.55014-1-mhun512@xxxxxxxxx/
>
> Found by static analysis on v7.2-rc2; not tested on hardware.

I understand you don't have Spectrum switches lying around to actually
test this out, but seeing the 'truea' typo... this _was_ at the very
least build-tested, right?