[PATCH v6 5/6] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy
From: Qiang Yu
Date: Wed Jul 22 2026 - 22:34:48 EST
Unlike Glymur, Mahua only has PCIe3b wired up; there is no PCIe3a
controller and no shared Gen5x8 PHY block. Delete the inherited pcie3a
and pcie3_phy nodes, and add a dedicated pcie3b_phy using the existing
qcom,glymur-qmp-gen5x4-pcie-phy compatible.
Point pcie3b_port0's phys and the GCC pipe clock parent array at
&pcie3b_phy instead of the deleted &pcie3_phy.
Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/mahua.dtsi | 89 +++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi
index 22822b6b2e8b..3280eb96d61c 100644
--- a/arch/arm64/boot/dts/qcom/mahua.dtsi
+++ b/arch/arm64/boot/dts/qcom/mahua.dtsi
@@ -22,6 +22,8 @@
/delete-node/ &cpu_pd16;
/delete-node/ &cpu_pd17;
/delete-node/ &cti_wpss;
+/delete-node/ &pcie3_phy;
+/delete-node/ &pcie3a;
/delete-node/ &thermal_aoss_6;
/delete-node/ &thermal_aoss_7;
/delete-node/ &thermal_cpu_2_0_0;
@@ -79,6 +81,52 @@ &config_noc {
compatible = "qcom,mahua-cnoc-cfg";
};
+&gcc {
+ clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */
+ <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */
+ <&sleep_clk>, /* Sleep */
+ <0>, /* USB 0 Phy DP0 GMUX */
+ <0>, /* USB 0 Phy DP1 GMUX */
+ <0>, /* USB 0 Phy PCIE PIPEGMUX */
+ <0>, /* USB 0 Phy PIPEGMUX */
+ <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */
+ <0>, /* USB 1 Phy DP0 GMUX 2 */
+ <0>, /* USB 1 Phy DP1 GMUX 2 */
+ <0>, /* USB 1 Phy PCIE PIPEGMUX */
+ <0>, /* USB 1 Phy PIPEGMUX */
+ <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */
+ <0>, /* USB 2 Phy DP0 GMUX 2 */
+ <0>, /* USB 2 Phy DP1 GMUX 2 */
+ <0>, /* USB 2 Phy PCIE PIPEGMUX */
+ <0>, /* USB 2 Phy PIPEGMUX */
+ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */
+ <0>, /* PCIe 3a pipe */
+ <&pcie3b_phy>, /* PCIe 3b pipe */
+ <&pcie4_phy>, /* PCIe 4 */
+ <&pcie5_phy>, /* PCIe 5 */
+ <&pcie6_phy>, /* PCIe 6 */
+ <0>, /* QUSB4 0 PHY RX 0 */
+ <0>, /* QUSB4 0 PHY RX 1 */
+ <0>, /* QUSB4 1 PHY RX 0 */
+ <0>, /* QUSB4 1 PHY RX 1 */
+ <0>, /* QUSB4 2 PHY RX 0 */
+ <0>, /* QUSB4 2 PHY RX 1 */
+ <0>, /* UFS PHY RX Symbol 0 */
+ <0>, /* UFS PHY RX Symbol 1 */
+ <0>, /* UFS PHY TX Symbol 0 */
+ <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_mp_qmpphy0>, /* USB3 UNI PHY pipe 0 */
+ <&usb_mp_qmpphy1>, /* USB3 UNI PHY pipe 1 */
+ <0>, /* USB4 PHY 0 pcie pipe */
+ <0>, /* USB4 PHY 0 Max pipe */
+ <0>, /* USB4 PHY 1 pcie pipe */
+ <0>, /* USB4 PHY 1 Max pipe */
+ <0>, /* USB4 PHY 2 pcie */
+ <0>; /* USB4 PHY 2 Max */
+};
+
&hsc_noc {
compatible = "qcom,mahua-hscnoc";
};
@@ -115,6 +163,10 @@ &oobm_ss_noc {
compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc";
};
+&pcie3b_port0 {
+ phys = <&pcie3b_phy>;
+};
+
&pcie_east_anoc {
compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc";
};
@@ -134,6 +186,43 @@ &pcie_west_slv_noc {
compatible = "qcom,mahua-pcie-west-slv-noc";
};
+&soc {
+ pcie3b_phy: phy@1b90000 {
+ compatible = "qcom,glymur-qmp-gen5x4-pcie-phy";
+ reg = <0x0 0x01b90000 0x0 0x10000>;
+
+ clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>,
+ <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
+ <&tcsr TCSR_PCIE_3_CLKREF_EN>,
+ <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_3B_PIPE_CLK>,
+ <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ resets = <&gcc GCC_PCIE_3B_PHY_BCR>,
+ <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie3b_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+};
+
&system_noc {
compatible = "qcom,mahua-system-noc", "qcom,glymur-system-noc";
};
--
2.34.1