Re: [PATCH v6 3/6] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY

From: Manivannan Sadhasivam

Date: Thu Jul 23 2026 - 09:39:35 EST

On Wed, Jul 22, 2026 at 07:30:20PM -0700, Qiang Yu wrote:
> Glymur's PCIe3a and PCIe3b controllers share a single Gen5x8 QMP PHY block
> that can be bifurcated into two independent x4 links, rather than each
> controller owning its own dedicated PHY.
>

Both subject and description doesn't give an impression that this commit
basically adds PCIe PHY and Controller nodes. It goes deeply on the details of
the PHY wiring though...

> Add a pcie3_phy node describing the shared PHY block, add the missing
> PCIe3a controller node, and point both PCIe3a's and PCIe3b's port phys
> at &pcie3_phy (index 0 and 1 respectively) so each controller picks up
> its half of the bifurcated PHY. Update the GCC pipe clock parent array
> to reference the new PHY's clock outputs instead of the placeholders.
>
> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 336 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 334 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index f32af66a3f1c..6355499ee5e5 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -801,8 +801,8 @@ gcc: clock-controller@100000 {
> <0>, /* USB 2 Phy PCIE PIPEGMUX */
> <0>, /* USB 2 Phy PIPEGMUX */
> <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */
> - <0>, /* PCIe 3a */
> - <0>, /* PCIe 3b */
> + <&pcie3_phy 0>, /* PCIe 3a pipe */
> + <&pcie3_phy 1>, /* PCIe 3b pipe */
> <&pcie4_phy>, /* PCIe 4 */
> <&pcie5_phy>, /* PCIe 5 */
> <&pcie6_phy>, /* PCIe 6 */
> @@ -2330,6 +2330,62 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> };
> };
>
> + pcie3_phy: phy@f00000 {
> + compatible = "qcom,glymur-qmp-gen5x8-pcie-phy";
> + reg = <0x0 0x00f00000 0x0 0x10000>,
> + <0x0 0x00f10000 0x0 0x10000>;
> + reg-names = "port_a",
> + "port_b";
> +
> + clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>,
> + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
> + <&tcsr TCSR_PCIE_3_CLKREF_EN>,
> + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_3A_PIPE_CLK>,
> + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>,
> + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_3B_PIPE_CLK>,
> + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "rchng",
> + "pipe",
> + "phy_b_aux",
> + "cfg_ahb_b",
> + "rchng_b",
> + "pipe_b",
> + "pipediv2_b";
> +
> + resets = <&gcc GCC_PCIE_3A_PHY_BCR>,
> + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>,
> + <&gcc GCC_PCIE_3B_PHY_BCR>,
> + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>;
> + reset-names = "port_a",
> + "port_a_nocsr",
> + "port_b",
> + "port_b_nocsr";
> +
> + assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>, <100000000>;
> +
> + power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>,
> + <&gcc GCC_PCIE_3B_PHY_GDSC>;
> + power-domain-names = "port_a", "port_b";
> +
> + qcom,link-mode = <&tcsr 0x5000>;
> +
> + #clock-cells = <1>;
> + clock-output-names = "pcie3a_pipe_clk",
> + "pcie3b_pipe_clk";
> +
> + #phy-cells = <1>;
> +
> + status = "disabled";
> + };
> +
> usb_hs_phy: phy@fa0000 {
> compatible = "qcom,glymur-m31-eusb2-phy",
> "qcom,sm8750-m31-eusb2-phy";
> @@ -3711,6 +3767,8 @@ pcie3b_port0: pcie@0 {
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
>
> + phys = <&pcie3_phy 1>;
> +
> #address-cells = <3>;
> #size-cells = <2>;
> ranges;
> @@ -3722,6 +3780,280 @@ pcie3b_port0_ep: endpoint {
> };
> };
>
> + pcie3a: pci@1c10000 {

pcie@

> + device_type = "pci";
> + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> + reg = <0x0 0x01c10000 0x0 0x3000>,
> + <0x0 0x70000000 0x0 0xf20>,
> + <0x0 0x70000f40 0x0 0xa8>,
> + <0x0 0x70001000 0x0 0x4000>,
> + <0x0 0x70100000 0x0 0x100000>,
> + <0x0 0x01c13000 0x0 0x1000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config",
> + "mhi";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
> + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>,
> + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>,
> + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>;
> +
> + bus-range = <0 0xff>;

0x00

> +
> + dma-coherent;
> +
> + linux,pci-domain = <3>;
> + num-lanes = <8>;

Drop this property.

> +
> + operating-points-v2 = <&pcie3a_opp_table>;
> +
> + msi-map = <0x0 &gic_its 0xb0000 0x10000>;
> + iommu-map = <0x0 &pcie_smmu 0x30000 0x10000>;
> +
> + interrupts = <GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 942 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0",
> + "msi1",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7",
> + "global";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 0 848 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 0 849 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 0 850 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 0 851 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
> + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "noc_aggr";
> +
> + assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&pcie_west_anoc MASTER_PCIE_3A QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &pcie_west_slv_noc SLAVE_PCIE_3A QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "pcie-mem",
> + "cpu-pcie";
> +
> + resets = <&gcc GCC_PCIE_3A_BCR>,
> + <&gcc GCC_PCIE_3A_LINK_DOWN_BCR>;
> + reset-names = "pci",
> + "link_down";
> +
> + power-domains = <&gcc GCC_PCIE_3A_GDSC>;
> +
> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
> + 0x5555 0x5555 0x5555 0x5555>;
> + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
> + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
> +
> + status = "disabled";
> +
> + pcie3a_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /* GEN 1 x1 */
> + opp-2500000-1 {
> + opp-hz = /bits/ 64 <2500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <250000 1>;
> + opp-level = <1>;
> + };
> +
> + /* GEN 1 x2 */
> + opp-5000000-1 {
> + opp-hz = /bits/ 64 <5000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <500000 1>;
> + opp-level = <1>;
> + };
> +
> + /* GEN 1 x4 */
> + opp-10000000-1 {
> + opp-hz = /bits/ 64 <10000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1000000 1>;
> + opp-level = <1>;
> + };
> +
> + /* GEN 1 x8 */
> + opp-20000000-1 {
> + opp-hz = /bits/ 64 <20000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <2000000 1>;
> + opp-level = <1>;
> + };
> +
> + /* GEN 2 x1 */
> + opp-5000000-2 {
> + opp-hz = /bits/ 64 <5000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <500000 1>;
> + opp-level = <2>;
> + };
> +
> + /* GEN 2 x2 */
> + opp-10000000-2 {
> + opp-hz = /bits/ 64 <10000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1000000 1>;
> + opp-level = <2>;
> + };
> +
> + /* GEN 2 x4 */
> + opp-20000000-2 {
> + opp-hz = /bits/ 64 <20000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <2000000 1>;
> + opp-level = <2>;
> + };
> +
> + /* GEN 2 x8 */
> + opp-40000000-2 {
> + opp-hz = /bits/ 64 <40000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <4000000 1>;
> + opp-level = <2>;
> + };
> +
> + /* GEN 3 x1 */
> + opp-8000000-3 {
> + opp-hz = /bits/ 64 <8000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <984500 1>;
> + opp-level = <3>;
> + };
> +
> + /* GEN 3 x2 */
> + opp-16000000-3 {
> + opp-hz = /bits/ 64 <16000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1969000 1>;
> + opp-level = <3>;
> + };
> +
> + /* GEN 3 x4 */
> + opp-32000000-3 {
> + opp-hz = /bits/ 64 <32000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <3938000 1>;
> + opp-level = <3>;
> + };
> +
> + /* GEN 3 x8 */
> + opp-64000000-3 {
> + opp-hz = /bits/ 64 <64000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <7876000 1>;
> + opp-level = <3>;
> + };
> +
> + /* GEN 4 x1 */
> + opp-16000000-4 {
> + opp-hz = /bits/ 64 <16000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + opp-peak-kBps = <1969000 1>;
> + opp-level = <4>;
> + };
> +
> + /* GEN 4 x2 */
> + opp-32000000-4 {
> + opp-hz = /bits/ 64 <32000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + opp-peak-kBps = <3938000 1>;
> + opp-level = <4>;
> + };
> +
> + /* GEN 4 x4 */
> + opp-64000000-4 {
> + opp-hz = /bits/ 64 <64000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + opp-peak-kBps = <7876000 1>;
> + opp-level = <4>;
> + };
> +
> + /* GEN 4 x8 */
> + opp-128000000-4 {
> + opp-hz = /bits/ 64 <128000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + opp-peak-kBps = <15753000 1>;
> + opp-level = <4>;
> + };
> +
> + /* GEN 5 x1 */
> + opp-32000000-5 {
> + opp-hz = /bits/ 64 <32000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <3938000 1>;
> + opp-level = <5>;
> + };
> +
> + /* GEN 5 x2 */
> + opp-64000000-5 {
> + opp-hz = /bits/ 64 <64000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <7876000 1>;
> + opp-level = <5>;
> + };
> +
> + /* GEN 5 x4 */
> + opp-128000000-5 {
> + opp-hz = /bits/ 64 <128000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <15753000 1>;
> + opp-level = <5>;
> + };
> +
> + /* GEN 5 x8 */
> + opp-256000000-5 {
> + opp-hz = /bits/ 64 <256000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <31506000 1>;
> + opp-level = <5>;
> + };
> + };
> +
> + pcie3a_port0: pcie@0 {

Add pciclass compatible.

- Mani

--
மணிவண்ணன் சதாசிவம்