Re: [PATCH] pmdomains: mediatek: Avoid setting RTFF's CLK_DIS before NRESTORE

[Ulf Hansson]

On Thu, Jul 16, 2026 at 1:42 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@xxxxxxxxxxxxx> wrote:
>
> For the PCIE_PHY (also called PEXTP_PHY) type of RTFF hardware,
> there is special handling setting CLK_DIS before performing the
> NRESTORE sequence for resetting the RTFF and start sequencing
> from a clean state.
>
> That special handling, though, poses an issue in case the machine
> specific bootchain (bootloader in particular) ends up booting the
> kernel with both PCIe MAC and PHY enabled (not just power domains)
> as doing so will partially corrupt the PCIe MAC/PHY registers in
> an unpredictable manner, producing either an initialization fail
> in the PCI-Express drivers, or even a hard lockup!
>
> Resolve this by simply removing the special handling: in this case
> the bootchain, or remote processors, setting is getting honored by
> the later check for PWR_RTFF_SAVE_FLAG presence in the RTFF ctl
> register.
>
> Fixes: 9d02c94342b3 ("pmdomain: mediatek: Add support for RTFF Hardware in MT8196/MT6991")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>

Applied for fixes and by adding a stable tag, thanks!

Kind regards
Uffe


> ---
>  drivers/pmdomain/mediatek/mtk-pm-domains.c | 8 --------
>  1 file changed, 8 deletions(-)
>
> diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
> index f69cf69ba0f6..df8e93638e08 100644
> --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
> +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
> @@ -480,16 +480,8 @@ static int scpsys_ctl_pwrseq_on(struct scpsys_domain *pd)
>         if (ret < 0)
>                 return ret;
>
> -       if (pd->data->rtff_type == SCPSYS_RTFF_TYPE_PCIE_PHY)
> -               regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RTFF_CLK_DIS);
> -
>         regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
>         regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
> -
> -       /* Wait for RTFF HW to sync buck isolation state if this is PCIe PHY RTFF */
> -       if (pd->data->rtff_type == SCPSYS_RTFF_TYPE_PCIE_PHY)
> -               udelay(5);
> -
>         regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
>
>         /*
> --
> 2.54.0
>