[PATCH RFC] drm/nouveau: Use write-combined maps for coherent on Tegra

[Aaron Kling via B4 Relay]

From: Faith Ekstrand <faith.ekstrand@xxxxxxxxxxxxx>

On Tegra devices, uncached maps traslate to device memory, causing
unaligned accesses by userspace resulting in a SIGBUS. Instead, use
write-combined maps to ensure proper access.

Signed-off-by: Faith Ekstrand <faith.ekstrand@xxxxxxxxxxxxx>
Co-developed-by: Aaron Kling <webgeek1234@xxxxxxxxx>
Signed-off-by: Aaron Kling <webgeek1234@xxxxxxxxx>
---
This patch is marked RFC because there is not complete confidence that
the change is correct. Without this change, nouveau can easily hit
sigbus errors in Android UI rendering via nvk or running vulkan deqp
tests on Tegra. Changing coherent maps to use write-combined stops the
crashing, but it is unknown what the performance impact is, if any.
---
 drivers/gpu/drm/nouveau/nouveau_sgdma.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index fa3b4ebf38a83..10f6ef1c541bd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -72,9 +72,12 @@ nouveau_sgdma_create_ttm(struct ttm_buffer_object *bo, uint32_t page_flags)
 	struct nouveau_sgdma_be *nvbe;
 	enum ttm_caching caching;
 
-	if (nvbo->force_coherent)
-		caching = ttm_uncached;
-	else if (drm->agp.bridge)
+	if (nvbo->force_coherent) {
+		if (drm->client.device.info.platform == NV_DEVICE_INFO_V0_SOC)
+			caching = ttm_write_combined;
+		else
+			caching = ttm_uncached;
+	} else if (drm->agp.bridge)
 		caching = ttm_write_combined;
 	else
 		caching = ttm_cached;

---
base-commit: 1a1757b76427f6201bfe0bf1bea9f7574f332a93
change-id: 20260725-tegra-coherent-wc-19941d1a5a60

Best regards,
-- 
Aaron Kling <webgeek1234@xxxxxxxxx>